Cox; William D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cox; William D..The latest application filed is for "logic array devices having complex macro-cell architecture and methods facilitating use of same".

Company Profile

0.20.14

Cox; William D. - Chapel Hill NC
Cox; William D - Chapel Hill NC
Cox; William D. - San Jose CA
Cox; William D. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Via configurable architecture for customization of analog circuitry in a semiconductor device Grant 7,972,907 - Kemerling , et al. July 5, 2	2011-07-05
Using selectable in-line inverters to reduce the number of inverters in a semiconductor design Grant 7,930,670 - Cox April 19, 2	2011-04-19
Configuring structured ASIC fabric using two non-adjacent via layers Grant 7,692,309 - Cox April 6, 2	2010-04-06
Via configurable architecture for customization of analog circuitry in a semiconductor device Grant 7,626,272 - Kemerling , et al. December 1, 2	2009-12-01
Configurable integrated circuit capacitor array using via mask layers Grant 7,595,229 - Ihme , et al. September 29, 2	2009-09-29
Logic Array Devices Having Complex Macro-cell Architecture And Methods Facilitating Use Of Same App 20090210848 - COX; William D.	2009-08-20
Logic array devices having complex macro-cell architecture and methods facilitating use of same Grant 7,538,580 - Cox May 26, 2	2009-05-26
Configuring Structured Asic Fabric Using Two Non-adjacent Via Layers App 20090065813 - COX; William D.	2009-03-12
Via Configurable Architecture For Customization Of Analog Circuitry In A Semiconductor Device App 20090061567 - Kemerling; James C. ; et al.	2009-03-05
Via Configurable Architecture For Customization Of Analog Circuitry In A Semiconductor Device App 20090032968 - Kemerling; James C. ; et al.	2009-02-05
VIA configurable architecture for customization of analog circuitry in a semiconductor device Grant 7,449,371 - Kemerling , et al. November 11, 2	2008-11-11
Creating high-drive logic devices from standard gates with minimal use of custom masks Grant 7,378,874 - Bharath , et al. May 27, 2	2008-05-27
Configurable Integrated Circuit Capacitor Array Using Via Mask Layers App 20080108201 - Ihme; David ; et al.	2008-05-08
Creating High-drive Logic Devices From Standard Gates With Minimal Use Of Custom Masks App 20080054939 - BHARATH; Bhaskar ; et al.	2008-03-06
Configurable integrated circuit capacitor array using via mask layers Grant 7,335,966 - Ihme , et al. February 26, 2	2008-02-26
Customization of structured ASIC devices using pre-process extraction of routing information Grant 7,334,208 - Cox February 19, 2	2008-02-19
Logic Array Devices Having Complex Macro-cell Architecture And Methods Facilitating Use Of Same App 20070262789 - COX; William D.	2007-11-15
Logic array devices having complex macro-cell architecture and methods facilitating use of same Grant 7,248,071 - Cox July 24, 2	2007-07-24
Via Configurable Architecture For Customization Of Analog Circuitry In A Semiconductor Device App 20050224982 - Kemerling, James C. ; et al.	2005-10-13
Configurable Integrated Circuit Capacitor Array Using Via Mask Layers App 20050189614 - Ihme, David ; et al.	2005-09-01
Logic array devices having complex macro-cell architecture and methods facilitating use of same App 20050117436 - Cox, William D.	2005-06-02
Logic array devices having complex macro-cell architecture and methods facilitating use of same Grant 6,873,185 - Cox March 29, 2	2005-03-29
Distributed RAM in a logic array Grant 6,693,454 - Cox February 17, 2	2004-02-17
Logic array devices having complex macro-cell architecture and methods facilitating use of same App 20030234666 - Cox, William D.	2003-12-25
Method and apparatus for testing a logic cell in a semiconductor device App 20030229837 - Cox, William D.	2003-12-11
Distributed Ram In A Logic Array App 20030214322 - Cox, William D.	2003-11-20
Cell architecture to reduce customization in a semiconductor device Grant 6,580,289 - Cox June 17, 2	2003-06-17
Cell architecture to reduce customization in a semiconductor device App 20020186045 - Cox, William D.	2002-12-12
Interface cell for a programmable integrated circuit employing antifuses Grant 5,900,742 - Kolze , et al. May 4, 1	1999-05-04
Logic module for field programmable gate array Grant 5,682,106 - Cox , et al. October 28, 1	1997-10-28
Programmed programmable device and method for programming antifuses of a programmable device Grant 5,544,070 - Cox , et al. August 6, 1	1996-08-06
Select set-based technology mapping method and apparatus Grant 5,526,276 - Cox , et al. June 11, 1	1996-06-11
Programmable application specific integrated circuit and logic cell therefor Grant 5,416,367 - Chan , et al. May 16, 1	1995-05-16
Field programmable antifuse device and programming method therefor Grant 5,327,024 - Cox July 5, 1	1994-07-05

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