Cowan; Joseph W.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Cowan; Joseph W..The latest application filed is for "net segment analyzer for chip cad layout".
- Cowan; Joseph W. - West Linn OR
- Cowan; Joseph W. - Durham NC
Trademarks
| Patent | Date |
|---|---|
| Grounding mechanism for semiconductor devices Grant 6,864,563 - Cowan March 8, 2 | 2005-03-08 |
| Net segment analyzer for chip CAD layout Grant 6,817,004 - Cowan , et al. November 9, 2 | 2004-11-09 |
| Net segment analyzer for chip CAD layout App 20040143809 - Cowan, Joseph W. ; et al. | 2004-07-22 |
| Device under interface card with on-board testing Grant 6,747,473 - Cowan June 8, 2 | 2004-06-08 |
| Device under test interface card with on-board testing App 20040059971 - Cowan, Joseph W. | 2004-03-25 |
| Interconnector and method of connecting probes to a die for functional analysis Grant 6,605,951 - Cowan August 12, 2 | 2003-08-12 |
| Grounded packaged semiconductor structure and manufacturing method therefor Grant 6,140,581 - Cowan , et al. October 31, 2 | 2000-10-31 |
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