loadpatents
name:-0.012720823287964
name:-0.021042108535767
name:-0.00047111511230469
Coteus; Paul William Patent Filings

Coteus; Paul William

Patent Applications and Registrations

Patent applications and USPTO patent grants for Coteus; Paul William.The latest application filed is for "data capture technique for hgh speed signaling".

Company Profile
0.21.10
  • Coteus; Paul William - Yorktown Heights NY US
  • Coteus; Paul William - Yorktwon Heights NY
  • Coteus; Paul William - Yorktown NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Variable voltage CMOS off-chip driver and receiver circuits
Grant 8,604,828 - Bickford , et al. December 10, 2
2013-12-10
Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof
Grant 7,684,224 - Bernstein , et al. March 23, 2
2010-03-23
Data Capture Technique For Hgh Speed Signaling
App 20090028073 - Barrett; Wayne Melvin ;   et al.
2009-01-29
Data capture technique for high speed signaling
Grant 7,418,068 - Barrett , et al. August 26, 2
2008-08-26
Pin grid array zero insertion force connectors configurable for supporting large pin counts
Grant 7,402,053 - Hougham , et al. July 22, 2
2008-07-22
Three-dimensional Architecture For Self-checking And Self-repairing Integrated Circuits
App 20080165521 - BERNSTEIN; KERRY ;   et al.
2008-07-10
Pin Grid Array Zero Insertion Force Connectors Configurable For Supporting Large Pin Counts
App 20080026627 - Hougham; Gareth Geoffrey ;   et al.
2008-01-31
Pin Grid Array Zero Insertion Force Connectors Configurable for Supporting Large Pin Counts
App 20080026628 - Hougham; Gareth Geoffrey ;   et al.
2008-01-31
Pin grid array zero insertion force connectors configurable for supporting large pin counts
Grant 7,322,844 - Hougham , et al. January 29, 2
2008-01-29
Structure Comprising 3-dimensional Integrated Circuit Architecture, Circuit Structure, And Instructions For Fabrication Thereof
App 20070283298 - Bernstein; Kerry ;   et al.
2007-12-06
Address wrap function for addressable memory devices
Grant 7,061,821 - Coteus , et al. June 13, 2
2006-06-13
Stress accommodation in electronic device interconnect technology for millimeter contact locations
Grant 6,919,515 - Blackshear , et al. July 19, 2
2005-07-19
Output driver impedance control for addressable memory devices
App 20050002223 - Coteus, Paul William ;   et al.
2005-01-06
Data capture technique for high speed signaling
App 20040114698 - Barrett, Wayne Melvin ;   et al.
2004-06-17
AC drive cross point adjust method and apparatus
Grant 6,518,794 - Coteus , et al. February 11, 2
2003-02-11
Address wrap function for addressable memory devices
App 20020108013 - Coteus, Paul William ;   et al.
2002-08-08
AC drive cross point adjust method and apparatus
App 20010038106 - Coteus, Paul William ;   et al.
2001-11-08
Smart memory interface
Grant 6,292,903 - Coteus , et al. September 18, 2
2001-09-18
Clustered, buffered simms and assemblies thereof
Grant 6,276,844 - Coteus , et al. August 21, 2
2001-08-21
Stress accommodation in electronic device interconnect technology for millimeter contact locations
App 20010004943 - Blackshear, Edmund David ;   et al.
2001-06-28
Memory cards with symmetrical pinout for back-to-back mounting in computer system
Grant 6,202,110 - Coteus , et al. March 13, 2
2001-03-13
Dynamic line termination clamping circuit
Grant 6,127,840 - Coteus , et al. October 3, 2
2000-10-03
Sinusoidal clock signal distribution using resonant transmission lines
Grant 6,098,176 - Coteus , et al. August 1, 2
2000-08-01
Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits
Grant 6,060,905 - Bickford , et al. May 9, 2
2000-05-09
Hinge incorporating a helically coiled heat pipe for a laptop computer
Grant 5,910,883 - Cipolla , et al. June 8, 1
1999-06-08
Method for providing a selective reference layer isolation technique for the production of printed circuit boards
Grant 5,863,447 - Coteus , et al. January 26, 1
1999-01-26
Method and system for detecting the presence of adapter cards
Grant 5,786,769 - Coteus , et al. July 28, 1
1998-07-28
Lead frame package for electronic devices
Grant 5,780,925 - Cipolla , et al. July 14, 1
1998-07-14
Removable heat sink assembly process for a chip package
Grant 5,771,559 - Cipolla , et al. June 30, 1
1998-06-30
Interchangeable key card edge connecting
Grant 5,688,147 - Coteus , et al. November 18, 1
1997-11-18

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed