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name:-0.017935991287231
name:-0.013386964797974
name:-0.0013730525970459
Coteus; Paul Patent Filings

Coteus; Paul

Patent Applications and Registrations

Patent applications and USPTO patent grants for Coteus; Paul.The latest application filed is for "computer system wafer integrating different dies in stacked master-slave structures".

Company Profile
0.11.12
  • Coteus; Paul - Yorktown NY
  • Coteus; Paul - Yorktown Heights NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Planar array contact memory cards
Grant 8,138,592 - Coteus , et al. March 20, 2
2012-03-20
Computer system wafer integrating different dies in stacked master-slave structures
App 20110272788 - Kim; Kyu-hyoun ;   et al.
2011-11-10
Method of making a land-grid-array (LGA) interposer
Grant 7,975,379 - Hougham , et al. July 12, 2
2011-07-12
Wafer level I/O test, repair and/or customization enabled by I/O layer
Grant 7,913,202 - Bernstein , et al. March 22, 2
2011-03-22
Compliant penetrating packaging interconnect
Grant 7,897,878 - Coteus , et al. March 1, 2
2011-03-01
Planar array contact memory cards
Grant 7,863,091 - Coteus , et al. January 4, 2
2011-01-04
Planar array contact memory cards
Grant 7,863,089 - Coteus , et al. January 4, 2
2011-01-04
Topography compensating land grid array interposer
App 20100173505 - Hougham; Gareth G. ;   et al.
2010-07-08
Planar array contact memory cards
Grant 7,566,959 - Coteus , et al. July 28, 2
2009-07-28
Wafer level I/O test and repair enabled by I/O layer
Grant 7,521,950 - Bernstein , et al. April 21, 2
2009-04-21
Planar Array Contact Memory Cards
App 20090072372 - COTEUS; Paul ;   et al.
2009-03-19
Planar Array Contact Memory Cards
App 20090075502 - COTEUS; Paul ;   et al.
2009-03-19
Compliant Penetrating Packaging Interconnect
App 20080180927 - Coteus; Paul ;   et al.
2008-07-31
Methods and apparatus using commutative error detection values for fault isolation in multiple node computers
Grant 7,383,490 - Almasi , et al. June 3, 2
2008-06-03
Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer
App 20080068039 - Bernstein; Kerry ;   et al.
2008-03-20
Planar Array Contact Memory Cards
App 20080045052 - Coteus; Paul ;   et al.
2008-02-21
Planar Array Contact Memory Cards
App 20080001275 - Coteus; Paul ;   et al.
2008-01-03
Planar array contact memory cards
Grant 7,282,790 - Coteus , et al. October 16, 2
2007-10-16
Wafer Level I/o Test And Repair Enabled By I/o Layer
App 20070081410 - Bernstein; Kerry ;   et al.
2007-04-12
Topography compensating land grid array interposer
App 20070054512 - Hougham; Gareth G. ;   et al.
2007-03-08
Planar array contact memory cards
App 20060274562 - Coteus; Paul ;   et al.
2006-12-07
Methods and apparatus using commutative error detection values for fault isolation in multiple node computers
App 20060248370 - Almasi; Gheorghe ;   et al.
2006-11-02
Elastic interface for master-slave communication
Grant 6,571,346 - Dreps , et al. May 27, 2
2003-05-27

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