Cote; Jean-Fran.cedilla.ois

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cote; Jean-Fran.cedilla.ois.The latest application filed is for "method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby".

Company Profile

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Cote; Jean-Fran.cedilla.ois - Chelsea CA
Cote; Jean-Fran.cedilla.ois - Alymer CA
Cote; Jean-Fran.cedilla.ois - Aylmer CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby Grant 6,868,532 - Nadeau-Dostie , et al. March 15, 2	2005-03-15
Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same Grant 6,829,730 - Nadeau-Dostie , et al. December 7, 2	2004-12-07
Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description Grant 6,763,489 - Nadeau-Dostie , et al. July 13, 2	2004-07-13
Test access circuit and method of accessing embedded test controllers in integrated circuit modules Grant 6,760,874 - Cote , et al. July 6, 2	2004-07-06
Method for collecting failure information for a memory using an embedded test controller Grant 6,738,938 - Nadeau-Dostie , et al. May 18, 2	2004-05-18
Method and program product for completing a circuit design having embedded test structures Grant 6,725,435 - Cote , et al. April 20, 2	2004-04-20
Self-contained embedded test design environment and environment setup utility Grant 6,678,875 - Pajak , et al. January 13, 2	2004-01-13
Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith Grant 6,671,839 - Cote , et al. December 30, 2	2003-12-30
Fault insertion method, boundary scan cells, and integrated circuit for use therewith Grant 6,536,008 - Nadeau-Dostie , et al. March 18, 2	2003-03-18
Method and apparatus for controlling power level during BIST Grant 6,330,681 - Cote , et al. December 11, 2	2001-12-11
Method of testing at-speed circuits having asynchronous clocks and controller for use therewith Grant 6,327,684 - Nadeau-Dostie , et al. December 4, 2	2001-12-04

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