Costello; Philip D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Costello; Philip D..The latest application filed is for "method of reducing power of a circuit".

Company Profile

0.18.0

Costello; Philip D. - Saratoga CA
Costello; Philip D. - San Jose CA
Costello; Philip D. - Sunnyvale IE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of reducing power of a circuit Grant 7,653,891 - Anderson , et al. January 26, 2	2010-01-26
Method for simulation of negative bias and temperature instability Grant 7,600,204 - Chirania , et al. October 6, 2	2009-10-06
Process monitor vehicle Grant 7,518,394 - Chirania , et al. April 14, 2	2009-04-14
Data monitoring for single event upset in a programmable logic device Grant 7,283,409 - Voogel , et al. October 16, 2	2007-10-16
Programmable lookup table with dual input and output terminals in RAM mode Grant 7,265,576 - Kondapalli , et al. September 4, 2	2007-09-04
Programmable logic block providing carry chain with programmable initialization values Grant 7,256,612 - Young , et al. August 14, 2	2007-08-14
Programmable lookup table with dual input and output terminals in shift register mode Grant 7,215,138 - Kondapalli , et al. May 8, 2	2007-05-08
High speed configurable transceiver architecture Grant 7,187,709 - Menon , et al. March 6, 2	2007-03-06
Data monitoring for single event upset in a programmable logic device Grant 7,109,746 - Voogel , et al. September 19, 2	2006-09-19
Method and apparatus for voltage regulation within an integrated circuit Grant 7,109,783 - Kondapalli , et al. September 19, 2	2006-09-19
Programmable circuit optionally configurable as a lookup table or a wide multiplexer Grant 7,075,333 - Chaudhary , et al. July 11, 2	2006-07-11
Low jitter clock for a physical media access sublayer on a field programmable gate array Grant 6,911,842 - Ghia , et al. June 28, 2	2005-06-28
Single event upset in SRAM cells in FPGAs with leaky gate transistors Grant 6,822,894 - Costello , et al. November 23, 2	2004-11-23
Method and apparatus for voltage regulation within an integrated circuit Grant 6,753,722 - Kondapalli , et al. June 22, 2	2004-06-22
High speed bus with tree structure for selecting bus driver Grant 5,936,424 - Young , et al. August 10, 1	1999-08-10
Write-assisted memory cell and method of operating same Grant 5,764,564 - Frake , et al. June 9, 1	1998-06-09
Buffer circuit having high stability and low quiescent current consumption Grant 5,216,291 - Seevinck , et al. June 1, 1	1993-06-01
Reference generator for generating a reference voltage and a reference current Grant 5,173,656 - Seevinck , et al. December 22, 1	1992-12-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.