loadpatents
name:-0.00049996376037598
name:-0.025820016860962
name:-0.0021378993988037
Cory; Warren E. Patent Filings

Cory; Warren E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cory; Warren E..The latest application filed is for "low latency data transfer technique for mesochronous divided clocks".

Company Profile
2.22.0
  • Cory; Warren E. - Redwood City CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Low latency data transfer technique for mesochronous divided clocks
Grant 10,623,174 - Remla , et al.
2020-04-14
Circuit for and method of providing a programmable connector of an integrated circuit device
Grant 10,528,513 - Chan , et al. J
2020-01-07
Circuits for and methods of transmitting data in an integrated circuit
Grant 10,038,450 - Cory July 31, 2
2018-07-31
Circuit for and method of measuring latency in an integrated circuit
Grant 10,033,523 - Remla , et al. July 24, 2
2018-07-24
Method and apparatus for a reduced lane-lane skew, low-latency transmission system
Grant 8,411,703 - Cory April 2, 2
2013-04-02
Error checking parity and syndrome of a block of data with relocated parity bits
Grant 8,301,988 - Cory , et al. October 30, 2
2012-10-30
Error checking parity and syndrome of a block of data with relocated parity bits
Grant 8,245,102 - Cory , et al. August 14, 2
2012-08-14
Method and apparatus for receive channel data alignment with minimized latency variation
Grant 7,913,104 - Cory , et al. March 22, 2
2011-03-22
Error checking parity and syndrome of a block of data with relocated parity bits
Grant 7,895,509 - Cory , et al. February 22, 2
2011-02-22
Method and system for pipelined decryption
Grant 7,623,660 - Cory November 24, 2
2009-11-24
Variable latency buffer and method of operation
Grant 7,519,747 - Cory , et al. April 14, 2
2009-04-14
Error checking parity and syndrome of a block of data with relocated parity bits
Grant 7,426,678 - Cory , et al. September 16, 2
2008-09-16
Channel bonding control logic architecture
Grant 7,382,823 - Cory June 3, 2
2008-06-03
Distributed adaptive channel bonding control for improved tolerance of inter-channel skew
Grant 7,295,639 - Cory November 13, 2
2007-11-13
High speed configurable transceiver architecture
Grant 7,187,709 - Menon , et al. March 6, 2
2007-03-06
Network physical layer with embedded multi-standard CRC generator
Grant 7,111,220 - Sasaki , et al. September 19, 2
2006-09-19
Flexible channel bonding and clock correction operations on a multi-block data path
Grant 7,099,426 - Cory , et al. August 29, 2
2006-08-29
Method and apparatus for operating a transceiver in different data rates
Grant 7,088,767 - Cory August 8, 2
2006-08-08
Variable data width converter
Grant 6,970,013 - Cory November 29, 2
2005-11-29
Variable data width operation in multi-gigabit transceivers on a programmable logic device
Grant 6,960,933 - Cory , et al. November 1, 2
2005-11-01
Variable data width operation in multi-gigabit transceivers on a programmable logic device
Grant 6,617,877 - Cory , et al. September 9, 2
2003-09-09

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