Correale, Jr.; Anthony

Patent Applications and Registrations

Patent applications and USPTO patent grants for Correale, Jr.; Anthony.The latest application filed is for "power distribution networks (pdns) using hybrid grid and pillar arrangements".

Company Profile

11.67.27

Correale, Jr.; Anthony - Raleigh NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Power efficient voltage level translator circuit Grant 11,223,359 - Nadkarni , et al. January 11, 2	2022-01-11
Integrated circuit (IC) design methods using engineering change order (ECO) cell architectures Grant 10,678,988 - Correale, Jr. , et al.	2020-06-09
Power distribution networks (PDNs) using hybrid grid and pillar arrangements Grant 10,380,308 - Correale, Jr. , et al. A	2019-08-13
Standard cell architecture for diffusion based on fin count Grant 10,366,196 - Correale, Jr. , et al. July 30, 2	2019-07-30
POWER DISTRIBUTION NETWORKS (PDNs) USING HYBRID GRID AND PILLAR ARRANGEMENTS App 20190213298 - Correale, JR.; Anthony ; et al.	2019-07-11
Integrated Circuit (ic) Design Methods Using Engineering Change Order (eco) Cell Architectures App 20190188353 - Correale, JR.; Anthony ; et al.	2019-06-20
Engineering Change Order (eco) Cell Architecture And Implementation App 20190138682 - Correale, JR.; Anthony ; et al.	2019-05-09
Mitigating length-of-diffusion effect for logic cells and placement thereof Grant 10,282,503 - Bowers , et al.	2019-05-07
Standard cell architecture for diffusion based on fin count Grant 10,236,302 - Correale, Jr. , et al.	2019-03-19
Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods Grant 9,978,682 - Correale, Jr. , et al. May 22, 2	2018-05-22
Mitigating Length-of-diffusion Effect For Logic Cells And Placement Thereof App 20170371994 - BOWERS; Benjamin John ; et al.	2017-12-28
Standard Cell Architecture For Diffusion Based On Fin Count App 20170371995 - CORREALE, JR.; Anthony ; et al.	2017-12-28
Standard Cell Architecture For Diffusion Based On Fin Count App 20170373090 - CORREALE, JR.; Anthony ; et al.	2017-12-28
Power Efficient Voltage Level Translator Circuit App 20170288673 - NADKARNI; Rahul Krishnakumar ; et al.	2017-10-05
Compiler for closed-loop 1.times.N VLSI design Grant 9,558,308 - Bowers , et al. January 31, 2	2017-01-31
Compiler For Closed-loop 1xn Vlsi Design App 20150169792 - Bowers; Benjamin J. ; et al.	2015-06-18
Compiler for closed-loop 1xN VLSI design Grant 8,887,113 - Bowers , et al. November 11, 2	2014-11-11
Compiler for closed-loop 1.times.N VLSI design Grant 8,739,086 - Bowers , et al. May 27, 2	2014-05-27
Creating integrated circuit capacitance from gate array structures Grant 8,298,888 - Correale, Jr. , et al. October 30, 2	2012-10-30
Compiler for Closed-Loop 1xN VLSI Design App 20120192128 - Bowers; Benjamin J. ; et al.	2012-07-26
Creating Integrated Circuit Capacitance From Gate Array Structures App 20120190165 - Correale, JR.; Anthony ; et al.	2012-07-26
Compiler for Closed-Loop 1xN VLSI Design App 20120192129 - Bowers; Benjamin J. ; et al.	2012-07-26
Creating integrated circuit capacitance from gate array structures Grant 8,188,516 - Correale, Jr. , et al. May 29, 2	2012-05-29
Uniquification and parent-child constructs for 1xN VLSI design Grant 8,156,458 - Baker , et al. April 10, 2	2012-04-10
Integrated design for manufacturing for 1.times.N VLSI design Grant 8,141,016 - Correale, Jr. , et al. March 20, 2	2012-03-20
Hierarchy reassembler for 1.times.N VLSI design Grant 8,136,062 - Steinmetz , et al. March 13, 2	2012-03-13
Closed-loop 1.times.N VLSI design system Grant 8,132,134 - Correale, Jr. , et al. March 6, 2	2012-03-06
Compiler for closed-loop 1.times.N VLSI design Grant 8,122,399 - Bowers , et al. February 21, 2	2012-02-21
Top level hierarchy wiring via 1.times.N compiler Grant 7,966,598 - Polomik , et al. June 21, 2	2011-06-21
Adaptive execution cycle control method for enhanced instruction throughput Grant 7,937,568 - Correale, Jr. , et al. May 3, 2	2011-05-03
Interconnect components of a semiconductor device Grant 7,919,819 - Correale, Jr. April 5, 2	2011-04-05
Systems and media to improve manufacturability of semiconductor devices Grant 7,908,571 - Bowers , et al. March 15, 2	2011-03-15
CMOS circuit leakage current calculator Grant 7,904,847 - Correale, Jr. , et al. March 8, 2	2011-03-08
Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank Grant 7,882,385 - Arnold , et al. February 1, 2	2011-02-01
System and method for creating a standard cell library for use in circuit designs Grant 7,784,012 - Correale, Jr. August 24, 2	2010-08-24
Adaptive execution frequency control method for enhanced instruction throughput Grant 7,779,237 - Correale, Jr. , et al. August 17, 2	2010-08-17
Systems and arrangements to interconnect components of a semiconductor device Grant 7,749,816 - Correale, Jr. July 6, 2	2010-07-06
Creating Integrated Circuit Capacitance from Gate Array Structures App 20100155800 - Correale, JR.; Anthony ; et al.	2010-06-24
Creating integrated circuit capacitance from gate array structures Grant 7,728,362 - Correale, Jr. , et al. June 1, 2	2010-06-01
1xn Block Builder For 1xn Vlsi Design App 20100107130 - Bowers; Benjamin J. ; et al.	2010-04-29
Closed-Loop 1xN VLSI Design System App 20100058271 - Correale, JR.; Anthony ; et al.	2010-03-04
Top Level Hierarchy Wiring Via 1xN Compiler App 20100058275 - Polomik; Anthony L. ; et al.	2010-03-04
Integrated Design for Manufacturing for 1xN VLSI Design App 20100058260 - Correale, Jr.; Anthony ; et al.	2010-03-04
Uniquification and Parent-Child Constructs for 1xN VLSI Design App 20100058269 - Baker; Matthew W. ; et al.	2010-03-04
Hierarchy Reassembler for 1xN VLSI Design App 20100058270 - Steinmetz; Paul M. ; et al.	2010-03-04
Compiler for Closed-Loop 1xN VLSI Design App 20100058272 - Bowers; Benjamin J. ; et al.	2010-03-04
System for blocking multiple memory read port activation Grant 7,672,188 - Correale, Jr. , et al. March 2, 2	2010-03-02
Apparatus for reducing leakage in global bit-line architectures Grant 7,619,923 - Correale, Jr. , et al. November 17, 2	2009-11-17
CMOS Circuit Leakage Current Calculator App 20090210831 - Correale, JR.; Anthony ; et al.	2009-08-20
System for Blocking Multiple Memory Read Port Activation App 20090154283 - Correale, JR.; Anthony ; et al.	2009-06-18
Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Modified Latch Bank App 20090150709 - Arnold; Nicole Marie ; et al.	2009-06-11
Apparatus For Reducing Leakage In Global Bit-line Architectures App 20090147590 - Correale, JR.; Anthony ; et al.	2009-06-11
Interconnect Components of a Semiconductor Device App 20090114952 - Correale, JR.; Anthony	2009-05-07
Scannable limited switch dynamic logic (LSDL) circuit Grant 7,501,850 - Correale, Jr. , et al. March 10, 2	2009-03-10
Influence-based circuit design Grant 7,500,207 - Bhattacharya , et al. March 3, 2	2009-03-03
Systems and arrangements to interconnect components of a semiconductor device Grant 7,492,013 - Correale, Jr. February 17, 2	2009-02-17
Multiple Voltage Integrated Circuit And Design Method Therefor App 20090032903 - Correale, JR.; Anthony ; et al.	2009-02-05
Multiple voltage integrated circuit and design method therefor Grant 7,480,883 - Correale, Jr. , et al. January 20, 2	2009-01-20
Adaptive Execution Cycle Control Method For Enhanced Instruction Throughput App 20090019264 - Correale, JR.; Anthony ; et al.	2009-01-15
Adaptive Execution Frequency Control Method For Enhanced Instruction Throughput App 20090019265 - CORREALE, JR.; ANTHONY ; et al.	2009-01-15
Cache organization for power optimized memory access Grant 7,475,192 - Correale, Jr. , et al. January 6, 2	2009-01-06
Dual damascene multi-level metallization Grant 7,470,613 - Agarwala , et al. December 30, 2	2008-12-30
Method and system for providing cache set selection which is power optimized Grant 7,395,372 - Correale, Jr. , et al. July 1, 2	2008-07-01
Methods, systems, and media to improve manufacturability of semiconductor devices Grant 7,343,570 - Bowers , et al. March 11, 2	2008-03-11
System and method for creating a standard cell library for reduced leakage and improved performance Grant 7,340,712 - Correale, Jr. March 4, 2	2008-03-04
Single supply level converter Grant 7,336,100 - Correale, Jr. , et al. February 26, 2	2008-02-26
Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Grant 7,290,226 - Correale, Jr. , et al. October 30, 2	2007-10-30
Speed verification of an embedded processor in a programmable logic device Grant 7,231,621 - Herron , et al. June 12, 2	2007-06-12
Dual-damascene metallization interconnection Grant 7,224,063 - Agarwala , et al. May 29, 2	2007-05-29
Single supply level converter Grant 7,119,578 - Correale, Jr. , et al. October 10, 2	2006-10-10
Multiple voltage integrated circuit and design method therefor Grant 7,111,266 - Correale, Jr. , et al. September 19, 2	2006-09-19
Voltage island circuit placement Grant 7,091,574 - Correale, Jr. August 15, 2	2006-08-15
Method and program product of level converter optimization Grant 7,089,510 - Correale, Jr. , et al. August 8, 2	2006-08-08
Testing a programmable logic device with embedded fixed logic using a scan chain Grant 7,080,300 - Herron , et al. July 18, 2	2006-07-18
Performance built-in self test system for a device and a method of use Grant 7,017,094 - Correale, Jr. , et al. March 21, 2	2006-03-21
Level translator circuit for power supply disablement Grant 6,900,662 - Correale, Jr. May 31, 2	2005-05-31
Level translator circuit for power supply disablement Grant 6,861,873 - Correale, Jr. March 1, 2	2005-03-01
Level translator circuit for use between circuits having distinct power supplies Grant 6,833,747 - Correale, Jr. December 21, 2	2004-12-21
Method and circuit for optimizing power consumption in a flip-flop Grant 6,831,495 - Correale, Jr. , et al. December 14, 2	2004-12-14
Circuit for preserving data in a flip-flop and a method of use Grant 6,762,638 - Correale, Jr. , et al. July 13, 2	2004-07-13
Method and circuit for optimizing power consumption and performance of driver circuits Grant 6,735,145 - Atallah , et al. May 11, 2	2004-05-11
Composite transistor having a slew-rate control Grant 6,670,683 - Bernstein , et al. December 30, 2	2003-12-30
Circuit for optimizing power consumption and performance Grant 6,657,912 - Correale, Jr. , et al. December 2, 2	2003-12-02
Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator Grant 6,603,339 - Atallah , et al. August 5, 2	2003-08-05
Precise and programmable duty cycle generator Grant 6,593,789 - Atallah , et al. July 15, 2	2003-07-15
Dynamic data bus allocation Grant 6,587,905 - Correale, Jr. , et al. July 1, 2	2003-07-01
Enhanced operational frequency for a precise and programmable duty cycle generator Grant 6,509,771 - Atallah , et al. January 21, 2	2003-01-21
Method and system for reducing power dissipation in a semiconductor storage device Grant 6,229,750 - Correale, Jr. , et al. May 8, 2	2001-05-08
Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits Grant 6,001,662 - Correale, Jr. , et al. December 14, 1	1999-12-14
Reduced power VLSI chip and driver circuit Grant 5,453,705 - Atallah , et al. September 26, 1	1995-09-26
By-pass boundary scan design Grant 5,042,034 - Correale, Jr. , et al. August 20, 1	1991-08-20
Memory by-pass for write through read operations Grant 4,998,221 - Correale, Jr. March 5, 1	1991-03-05