Convey Computer

Patent Applications and Registrations

Patent applications and USPTO patent grants for Convey Computer.The latest application filed is for "multiple data channel memory module architecture".

Company Profile

2.11.13

Convey Computer - Richardson TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems and methods for selectively controlling multithreaded execution of executable code segments Grant 10,430,190 - Leidel , et al. O	2019-10-01
Multistate development workflow for generating a custom instruction set reconfigurable processor Grant 10,223,081 - Brewer	2019-03-05
Multiple Data Channel Memory Module Architecture App 20150206561 - Brewer; Tony M. ; et al.	2015-07-23
Multistate Development Workflow For Generating A Custom Instruction Set Reconfigurable Processor App 20150143350 - Brewer; Tony	2015-05-21
Multiple data channel memory module architecture Grant 9,015,399 - Brewer , et al. April 21, 2	2015-04-21
Multistage development workflow for generating a custom instruction set reconfigurable processor Grant 8,972,958 - Brewer March 3, 2	2015-03-03
Systems And Methods For Efficient Scheduling Of Concurrent Applications In Multithreaded Processors App 20130332711 - Leidel; John D. ; et al.	2013-12-12
Compiler for generating an executable comprising instructions for a plurality of different instruction sets Grant 8,561,037 - Wallach , et al. October 15, 2	2013-10-15
Memory interleave for heterogeneous computing Grant 8,443,147 - Brewer , et al. May 14, 2	2013-05-14
Systems and methods for mapping a neighborhood of data to general registers of a processing element Grant 8,423,745 - Brewer April 16, 2	2013-04-16
Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor Grant 8,205,066 - Brewer , et al. June 19, 2	2012-06-19
Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set Grant 8,156,307 - Wallach , et al. April 10, 2	2012-04-10
Memory Interleave For Heterogeneous Computing App 20120079177 - BREWER; Tony M. ; et al.	2012-03-29
Dispatch mechanism for dispatching instructions from a host processor to a co-processor Grant 8,122,229 - Wallach , et al. February 21, 2	2012-02-21
Memory interleave for heterogeneous computing Grant 8,095,735 - Brewer , et al. January 10, 2	2012-01-10
Co-processor Infrastructure Supporting Dynamically-modifiable Personalities App 20100115237 - Brewer; Tony ; et al.	2010-05-06
Dynamically-selectable Vector Register Partitioning App 20100115233 - Brewer; Tony ; et al.	2010-05-06
Multiple Data Channel Memory Module Architecture App 20100036997 - Brewer; Tony M. ; et al.	2010-02-11
Memory Interleave For Heterogeneous Computing App 20100037024 - Brewer; Tony M. ; et al.	2010-02-11
Microprocessor Architecture Having Alternative Memory Access Paths App 20090177843 - Wallach; Steven J. ; et al.	2009-07-09
Dispatch Mechanism For Dispatching Insturctions From A Host Processor To A Co-processor App 20090070553 - Wallach; Steven J. ; et al.	2009-03-12
Compiler For Generating An Executable Comprising Instructions For A Plurality Of Different Instruction Sets App 20090064095 - Wallach; Steven J. ; et al.	2009-03-05
Multi-processor System Having At Least One Processor That Comprises A Dynamically Reconfigurable Instruction Set App 20090055596 - Wallach; Steven J. ; et al.	2009-02-26

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