Contiero; Claudio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Contiero; Claudio.The latest application filed is for "semiconductor device with buried conductive region, and method for manufacturing the semiconductor device".

Company Profile

0.14.1

Contiero; Claudio - Buccinasco IT
Contiero; Claudio - Milan IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device with buried metallic region, and method for manufacturing the semiconductor device Grant 10,062,757 - Toia , et al. August 28, 2	2018-08-28
Semiconductor Device With Buried Conductive Region, And Method For Manufacturing The Semiconductor Device App 20170250253 - Toia; Fabrizio Fausto Renzo ; et al.	2017-08-31
Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage Grant RE37,424 - Contiero , et al. October 30, 2	2001-10-30
Process for fabricating a high voltage MOSFET Grant 6,093,588 - De Petro , et al. July 25, 2	2000-07-25
Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells Grant 6,022,778 - Contiero , et al. February 8, 2	2000-02-08
Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground Grant 5,852,314 - Depetro , et al. December 22, 1	1998-12-22
Integrated circuit with EPROM cells Grant 5,837,554 - Contiero , et al. November 17, 1	1998-11-17
Integrated circuit with EPROM cells Grant 5,610,421 - Contiero , et al. March 11, 1	1997-03-11
VDMOS transistor with improved breakdown characteristics Grant 5,430,316 - Contiero , et al. July 4, 1	1995-07-04
Mixed technology integrated circuit comprising CMOS structures and efficient lateral bipolar transistors with a high early voltage and fabrication thereof Grant 5,081,517 - Contiero , et al. January 14, 1	1992-01-14
Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage Grant 5,041,895 - Contiero , et al. August 20, 1	1991-08-20
Monolithically integrated semiconductor device containing bipolar junction transistors, CMOS and DMOS transistors and low leakage diodes and a method for its fabrication Grant 4,887,142 - Bertotti , et al. December 12, 1	1989-12-12
Self-aligned process for fabricating small DMOS cells Grant 4,774,198 - Contiero , et al. September 27, 1	1988-09-27
Method for DMOS semiconductor device fabrication Grant 4,757,032 - Contiero July 12, 1	1988-07-12
Process for forming semiconductor device having multi-thickness metallization Grant 4,718,977 - Contiero , et al. January 12, 1	1988-01-12

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