| Patent | Date |
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Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
Grant 11,322,408 - Loubet , et al. May 3, 2 | 2022-05-03 |
Dual width finned semiconductor structure
Grant 11,189,532 - Song , et al. November 30, 2 | 2021-11-30 |
Nanosheet transistor having a strained channel with strain-preserving multi-segmented source/drain regions
Grant 11,164,958 - Mochizuki , et al. November 2, 2 | 2021-11-02 |
Middle-of-line interconnect having low metal-to-metal interface resistance
Grant 11,114,382 - Varghese , et al. September 7, 2 | 2021-09-07 |
Nanosheet Transistor Having A Strained Channel With Strain-preserving Multi-segmented Source/drain Regions
App 20210234020 - Mochizuki; Shogo ; et al. | 2021-07-29 |
Self-aligned gate contact integration with metal resistor
Grant 11,056,537 - Miao , et al. July 6, 2 | 2021-07-06 |
Nano Multilayer Carbon-rich Low-k Spacer
App 20210151579 - Canaperi; Donald ; et al. | 2021-05-20 |
Forming Shallow Trench Isolation Regions For Nanosheet Field-effect Transistor Devices Using Sacrificial Epitaxial Layer
App 20210111077 - Loubet; Nicolas ; et al. | 2021-04-15 |
Nano multilayer carbon-rich low-k spacer
Grant 10,937,892 - Canaperi , et al. March 2, 2 | 2021-03-02 |
Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
Grant 10,910,273 - Loubet , et al. February 2, 2 | 2021-02-02 |
Stress modulation of nFET and pFET fin structures
Grant 10,832,973 - Zhou , et al. November 10, 2 | 2020-11-10 |
Collision Mitigation Apparatus Material Testing Systems Having Collision Mitigation Apparatus
App 20200309651 - Conti; Richard A. ; et al. | 2020-10-01 |
Self-aligned Gate Contact Integration With Metal Resistor
App 20200312909 - Miao; Xin ; et al. | 2020-10-01 |
Forming Shallow Trench Isolation Regions For Nanosheet Field-effect Transistor Devices Using Sacrificial Epitaxial Layer
App 20200273753 - Loubet; Nicolas ; et al. | 2020-08-27 |
Stress Modulation Of Nfet And Pfet Fin Structures
App 20200266111 - Zhou; Huimei ; et al. | 2020-08-20 |
Highly selective dry etch process for vertical FET STI recess
Grant 10,734,245 - Bi , et al. | 2020-08-04 |
Dual Width Finned Semiconductor Structure
App 20200194314 - Song; Yi ; et al. | 2020-06-18 |
Dual width finned semiconductor structure
Grant 10,672,668 - Song , et al. | 2020-06-02 |
Stress modulation of nFET and pFET fin structures
Grant 10,665,512 - Zhou , et al. | 2020-05-26 |
Highly Selective Dry Etch Process for Vertical FET STI Recess
App 20200126805 - Bi; Zhenxing ; et al. | 2020-04-23 |
Stress Modulation Of Nfet And Pfet Fin Structures
App 20200126867 - Zhou; Huimei ; et al. | 2020-04-23 |
Middle-of-line Interconnect Having Low Metal-to-metal Interface Resistance
App 20200126926 - Varghese; Alex Joseph ; et al. | 2020-04-23 |
Nano Multilayer Carbon-rich Low-k Spacer
App 20200083345 - Canaperi; Donald ; et al. | 2020-03-12 |
Multi-level air gap formation in dual-damascene structure
Grant 10,586,733 - Conti , et al. | 2020-03-10 |
Protection of low temperature isolation fill
Grant 10,586,700 - Belyansky , et al. | 2020-03-10 |
Preventing Delamination At Silicon/dielectic Interface
App 20200051812 - Belyansky; Michael P. ; et al. | 2020-02-13 |
Protection of low temperature isolation fill
Grant 10,535,550 - Belyansky , et al. Ja | 2020-01-14 |
Dual Width Finned Semiconductor Structure
App 20190371678 - Song; Yi ; et al. | 2019-12-05 |
Multi-level Air Gap Formation In Dual-damascene Structure
App 20190157140 - Conti; Richard A. ; et al. | 2019-05-23 |
Multi-level air gap formation in dual-damascene structure
Grant 10,224,239 - Conti , et al. | 2019-03-05 |
Protection Of Low Temperature Isolation Fill
App 20190067079 - Belyansky; Michael P. ; et al. | 2019-02-28 |
Protection Of Low Temperature Isolation Fill
App 20190067078 - Belyansky; Michael P. ; et al. | 2019-02-28 |
Multi-level air gap formation in dual-damascene structure
Grant 10,204,827 - Conti , et al. Feb | 2019-02-12 |
Multi-level Air Gap Formation In Dual-damascene Structure
App 20180019200 - Conti; Richard A. ; et al. | 2018-01-18 |
Multi-level Air Gap Formation In Dual-damascene Structure
App 20180019202 - Conti; Richard A. ; et al. | 2018-01-18 |
Multi-level Air Gap Formation In Dual-damascene Structure
App 20180019203 - Conti; Richard A. ; et al. | 2018-01-18 |
Multi-level air gap formation in dual-damascene structure
Grant 9,859,212 - Conti , et al. January 2, 2 | 2018-01-02 |
Multilayer sidewall spacer for seam protection of a patterned structure
Grant 8,673,725 - O'Meara , et al. March 18, 2 | 2014-03-18 |
Dual sidewall spacer for seam protection of a patterned structure
Grant 8,664,102 - O'Meara , et al. March 4, 2 | 2014-03-04 |
Structure And Method For Reduction Of Vt-w Effect In High-k Metal Gate Devices
App 20130140670 - Aquilino; Michael V. ; et al. | 2013-06-06 |
Structure And Method For Reduction Of Vt-w Effect In High-k Metal Gate Devices
App 20120187522 - Aquilino; Michael V. ; et al. | 2012-07-26 |
Dual Sidewall Spacer For Seam Protection Of A Patterned Structure
App 20110241085 - O'Meara; David L. ; et al. | 2011-10-06 |
Multilayer Sidewall Spacer For Seam Protection Of A Patterned Structure
App 20110241128 - O'Meara; David L. ; et al. | 2011-10-06 |
Mask forming and implanting methods using implant stopping layer
Grant 7,998,871 - Babich , et al. August 16, 2 | 2011-08-16 |
Process of making a semiconductor device using multiple antireflective materials
Grant 7,968,270 - Angelopoulos , et al. June 28, 2 | 2011-06-28 |
Structure and method to control oxidation in high-k gate structures
Grant 7,955,926 - Natzle , et al. June 7, 2 | 2011-06-07 |
Method of forming nitride films with high compressive stress for improved PFET device performance
Grant 7,804,136 - Conti , et al. September 28, 2 | 2010-09-28 |
Mask forming and implanting methods using implant stopping layer and mask so formed
Grant 7,651,947 - Babich , et al. January 26, 2 | 2010-01-26 |
Method Of Fabricating A Gate Structure
App 20090311855 - Bruff; Richard A. ; et al. | 2009-12-17 |
Structure And Method To Control Oxidation In High-k Gate Structures
App 20090243031 - Natzle; Wesley C. ; et al. | 2009-10-01 |
Method Of Fabricating A Gate Structure And The Structure Thereof
App 20090101980 - Bruff; Richard A. ; et al. | 2009-04-23 |
Method of forming nitride films with high compressive stress for improved PFET device performance
Grant 7,491,660 - Conti , et al. February 17, 2 | 2009-02-17 |
Process of making a semiconductor device using multiple antireflective materials
Grant 7,485,573 - Angelopoulos , et al. February 3, 2 | 2009-02-03 |
Mask Forming And Implanting Methods Using Implant Stopping Layer
App 20090004869 - Babich; Katherina ; et al. | 2009-01-01 |
Process Of Making A Semiconductor Device Using Multiple Antireflective Materials
App 20080311508 - Angelopoulos; Marie ; et al. | 2008-12-18 |
Method of forming nitride films with high compressive stress for improved PFET device performance
Grant 7,462,527 - Conti , et al. December 9, 2 | 2008-12-09 |
Mask Having Implant Stopping Layer
App 20080286545 - Babich; Katherina ; et al. | 2008-11-20 |
HDP-based ILD capping layer
Grant 7,372,158 - Wang , et al. May 13, 2 | 2008-05-13 |
Method Of Forming Nitride Films With High Compressive Stress For Improved Pfet Device Performance
App 20080045039 - Conti; Richard A. ; et al. | 2008-02-21 |
Method Of Forming Nitride Films With High Compressive Stress For Improved Pfet Device Performance
App 20080036007 - Conti; Richard A. ; et al. | 2008-02-14 |
Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material
Grant 7,326,651 - Baks , et al. February 5, 2 | 2008-02-05 |
Mask Forming And Implanting Methods Using Implant Stopping Layer And Mask So Formed
App 20070275563 - Babich; Katherina ; et al. | 2007-11-29 |
Process of making a semiconductor device using multiple antireflective materials
App 20070196748 - Angelopoulos; Marie ; et al. | 2007-08-23 |
Method For Protecting A Semiconductor Device From Carbon Depletion Based Damage
App 20070048981 - Bonilla; Griselda ; et al. | 2007-03-01 |
Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same
Grant 7,179,760 - Conti , et al. February 20, 2 | 2007-02-20 |
Method Of Forming Nitride Films With High Compressive Stress For Improved Pfet Device Performance
App 20070007548 - Conti; Richard A. ; et al. | 2007-01-11 |
BILAYER CAP STRUCTURE INCLUDING HDP/bHDP FILMS FOR CONDUCTIVE METALLIZATION AND METHOD OF MAKING SAME
App 20060270245 - Conti; Richard A. ; et al. | 2006-11-30 |
HDP-based ILD capping layer
Grant 7,138,717 - Wang , et al. November 21, 2 | 2006-11-21 |
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
Grant 7,084,079 - Conti , et al. August 1, 2 | 2006-08-01 |
Improved Hdp-based Ild Capping Layer
App 20060113672 - Wang; Yun-Yu ; et al. | 2006-06-01 |
Self-aligned buried strap process using doped HDP oxide
Grant 6,946,345 - Beintner , et al. September 20, 2 | 2005-09-20 |
Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure
Grant 6,911,378 - Conti , et al. June 28, 2 | 2005-06-28 |
Method For Forming Damascene Structure Utilizing Planarizing Material Coupled With Compressive Diffusion Barrier Material
App 20050079701 - Baks, Heidi ; et al. | 2005-04-14 |
Stabilization Of Fluorine-containing Dielectric Materials In A Metal Insulator Wiring Structure
App 20040266140 - Conti, Richard A. ; et al. | 2004-12-30 |
Self-aligned buried strap process using doped HDP oxide
App 20040188740 - Beintner, Jochen ; et al. | 2004-09-30 |
Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
Grant 6,740,539 - Conti , et al. May 25, 2 | 2004-05-25 |
Self-aligned buried strap process using doped HDP oxide
Grant 6,667,504 - Beintner , et al. December 23, 2 | 2003-12-23 |
Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
App 20030153198 - Conti, Richard A. ; et al. | 2003-08-14 |
Modified gate processing for optimized definition of array and logic devices on same chip
Grant 6,548,357 - Weybright , et al. April 15, 2 | 2003-04-15 |
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
App 20030068853 - Conti, Richard A. ; et al. | 2003-04-10 |
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
Grant 6,531,412 - Conti , et al. March 11, 2 | 2003-03-11 |
Method For Low Temperature Chemical Vapor Deposition Of Low-k Films Using Selected Cyclosiloxane And Ozone Gases For Semiconductor Applications
App 20030032306 - Conti, Richard A. ; et al. | 2003-02-13 |
Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
App 20030017642 - Conti, Richard A. ; et al. | 2003-01-23 |
Methods and materials for depositing films on semiconductor substrates
Grant 6,500,772 - Chakravarti , et al. December 31, 2 | 2002-12-31 |
Low temperature carbon rich oxy-nitride for improved RIE selectivity
Grant 6,486,015 - Chaudhary , et al. November 26, 2 | 2002-11-26 |
Bis (tertiarybutylamino) silane and ozone based doped and undoped oxides
App 20020127883 - Conti, Richard A. ; et al. | 2002-09-12 |
Modified gate processing for optimized difinition of array and logic devices on same chip
App 20020111025 - Weybright, Mary E. ; et al. | 2002-08-15 |
Methods and materials for depositing films on semiconductor substrates
App 20020090835 - Chakravarti, Ashima B. ; et al. | 2002-07-11 |
Modified gate processing for optimized definition of array and logic devices on same chip
Grant 6,403,423 - Weybright , et al. June 11, 2 | 2002-06-11 |
Directional CVD process with optimized etchback
Grant 6,335,261 - Natzle , et al. January 1, 2 | 2002-01-01 |
Manufacturing of cavity fuses on gate conductor level
Grant 6,274,440 - Arndt , et al. August 14, 2 | 2001-08-14 |
Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
Grant 6,232,222 - Armacost , et al. May 15, 2 | 2001-05-15 |
Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill
Grant 6,159,870 - Chakravarti , et al. December 12, 2 | 2000-12-12 |
Methods and apparatus for filling high aspect ratio structures with silicate glass
Grant 6,077,786 - Chakravarti , et al. June 20, 2 | 2000-06-20 |
High throughput chemical vapor deposition process capable of filling high aspect ratio structures
Grant 6,030,881 - Papasouliotis , et al. February 29, 2 | 2000-02-29 |
Apparatus for chemical vapor deposition of aluminum oxide
Grant 5,614,247 - Barbee , et al. March 25, 1 | 1997-03-25 |
Fluid delivery apparatus and method having an infrared feedline sensor
Grant 5,492,718 - O'Neill , et al. February 20, 1 | 1996-02-20 |
Aluminum oxide low pressure chemical vapor deposition (LPCVD) system-fourier transform infrared (FTIR) source chemical control
Grant 5,431,734 - Chapple-Sokol , et al. July 11, 1 | 1995-07-11 |
Removable gas injectors for use in chemical vapor deposition of aluminium oxide
Grant 5,425,810 - Conti , et al. June 20, 1 | 1995-06-20 |
Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics
Grant 5,383,088 - Chapple-Sokol , et al. January 17, 1 | 1995-01-17 |
Safe method for etching silicon dioxide
Grant 5,268,069 - Chapple-Sokol , et al. December 7, 1 | 1993-12-07 |
LPCVD reactor for high efficiency, high uniformity deposition
Grant 5,134,963 - Barbee , et al. August 4, 1 | 1992-08-04 |
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