Conti; Dennis R.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Conti; Dennis R..The latest application filed is for "integrated circuit tester probe contact liner".
- Conti; Dennis R. - Essex Junction VT
| Patent | Date |
|---|---|
| Low force wafer test probe Grant 11,029,334 - Audette , et al. June 8, 2 | 2021-06-08 |
| Integrated circuit tester probe contact liner Grant 11,009,545 - Arvin , et al. May 18, 2 | 2021-05-18 |
| Integrated Circuit Tester Probe Contact Liner App 20200209308 - Arvin; Charles L. ; et al. | 2020-07-02 |
| Integrated circuit tester probe contact liner Grant 10,670,653 - Arvin , et al. | 2020-06-02 |
| Low force wafer test probe with variable geometry Grant 10,663,487 - Audette , et al. | 2020-05-26 |
| Low Force Wafer Test Probe App 20190361048 - Audette; David M. ; et al. | 2019-11-28 |
| Integrated Circuit Tester Probe Contact Liner App 20190353702 - Arvin; Charles L. ; et al. | 2019-11-21 |
| Low force wafer test probe Grant 10,444,260 - Audette , et al. Oc | 2019-10-15 |
| Low Force Wafer Test Probe With Variable Geometry App 20190195913 - Audette; David M. ; et al. | 2019-06-27 |
| Low force wafer test probe with variable geometry Grant 10,261,108 - Audette , et al. | 2019-04-16 |
| Pressing Solder Bumps To Match Probe Profile During Wafer Level Testing App 20180358321 - Audette; David M. ; et al. | 2018-12-13 |
| Pressing Solder Bumps To Match Probe Profile During Wafer Level Testing App 20180358323 - Audette; David M. ; et al. | 2018-12-13 |
| Pressing Solder Bumps To Match Probe Profile During Wafer Level Testing App 20180358322 - Audette; David M. ; et al. | 2018-12-13 |
| Low Force Wafer Test Probe With Variable Geometry App 20180017596 - Audette; David M. ; et al. | 2018-01-18 |
| Low Force Wafer Test Probe App 20180017592 - Audette; David M. ; et al. | 2018-01-18 |
| Programmable active thermal control Grant 9,152,517 - Chase , et al. October 6, 2 | 2015-10-06 |
| Programmable Active Thermal Control App 20120272100 - Chase; Harold ; et al. | 2012-10-25 |
| Device burn in utilizing voltage control Grant 7,265,561 - Conti , et al. September 4, 2 | 2007-09-04 |
| Device Burn In Utilizing Voltage Control App 20050068053 - Conti, Dennis R. ; et al. | 2005-03-31 |
| Applying parametric test patterns for high pin count ASICs on low pin count testers Grant 6,847,203 - Conti , et al. January 25, 2 | 2005-01-25 |
| Applying Parametric Test Patterns For High Pin Count Asics On Low Pin Count Testers App 20050001611 - Conti, Dennis R. ; et al. | 2005-01-06 |
| Segmented architecture for wafer test & burn-in App 20010050567 - Bachelder, Thomas W. ; et al. | 2001-12-13 |
| Segmented architecture for wafer test and burn-in Grant 6,275,051 - Bachelder , et al. August 14, 2 | 2001-08-14 |
| Method for choosing replacement lines in a two dimensionally redundant array Grant 4,751,656 - Conti , et al. June 14, 1 | 1988-06-14 |
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