Conn; Robert O.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Conn; Robert O..The latest application filed is for "in system reflow of low temperature eutectic bond balls".

Company Profile

0.66.18

Conn; Robert O. - Hakalau HI
Conn; Robert O. - San Jose CA
Conn; Robert O. - Laupahoehoe HI US
Conn; Robert O. - US
Conn; Robert O. - Hawaii HI
Conn; Robert O. - Los Gatos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Accelerator having acceleration channels formed between covalently bonded chips Grant 8,742,700 - Hailey , et al. June 3, 2	2014-06-03
In System Reflow of Low Temperature Eutectic Bond Balls App 20140144971 - Conn; Robert O. ; et al.	2014-05-29
Accelerator having acceleration channels formed between covalently bonded chips Grant 8,680,792 - Hailey , et al. March 25, 2	2014-03-25
In system reflow of low temperature eutectic bond balls Grant 8,671,560 - Conn , et al. March 18, 2	2014-03-18
Accelerator Having Acceleration Channels Formed Between Covalently Bonded Chips App 20140049193 - Hailey; Kim L. ; et al.	2014-02-20
Accelerator having a multi-channel micro-collimator Grant 8,648,315 - Hailey , et al. February 11, 2	2014-02-11
Accelerator on a chip having a grid and plate cell Grant 8,564,225 - Hailey , et al. October 22, 2	2013-10-22
Through-substrate via having a strip-shaped through-hole signal conductor Grant 8,541,884 - Conn , et al. September 24, 2	2013-09-24
Accelerator on a chip having a cold ion source Grant 8,541,757 - Hailey , et al. September 24, 2	2013-09-24
Accelerator having acceleration channels formed between covalently bonded chips Grant 8,519,644 - Hailey , et al. August 27, 2	2013-08-27
Preventing breakage of long metal signal conductors on semiconductor substrates Grant 8,404,585 - Conn March 26, 2	2013-03-26
Through-Substrate Via Having a Strip-Shaped Through-Hole Signal Conductor App 20130009322 - Conn; Robert O. ; et al.	2013-01-10
Integrated semiconductor substrate structure using incompatible processes Grant 8,222,086 - Conn July 17, 2	2012-07-17
Integral metal structure with conductive post portions Grant 8,129,834 - Conn March 6, 2	2012-03-06
Disabling unused/inactive resources in an integrated circuit for static power reduction Grant 8,099,691 - Tuan , et al. January 17, 2	2012-01-17
Interposer for redistributing signals Grant 8,062,968 - Conn November 22, 2	2011-11-22
Preventing breakage of long metal signal conductors on semiconductor substrates App 20110266034 - Conn; Robert O.	2011-11-03
In system reflow of low temperature eutectic bond balls App 20110239456 - Conn; Robert O. ; et al.	2011-10-06
Large substrate structural vias Grant 8,008,134 - Conn August 30, 2	2011-08-30
Preventing breakage of long metal signal conductors on semiconductor substrates Grant 7,999,388 - Conn August 16, 2	2011-08-16
Integrated semiconductor substrate structure using incompatible processes App 20110183469 - Conn; Robert O.	2011-07-28
Multiple-layer signal conductor Grant 7,978,029 - Conn July 12, 2	2011-07-12
Integrated semiconductor substrate structure using incompatible processes Grant 7,944,041 - Conn May 17, 2	2011-05-17
Multiple-layer signal conductor App 20100283559 - Conn; Robert O.	2010-11-11
Local defect memories on semiconductor substrates in a stack computer Grant 7,831,874 - Conn November 9, 2	2010-11-09
Semiconductor substrate elastomeric stack Grant 7,829,994 - Conn November 9, 2	2010-11-09
Large substrate structural vias App 20100200540 - Conn; Robert O.	2010-08-12
Integral metal structure with conductive post portions App 20100187665 - Conn; Robert O.	2010-07-29
Comb-shaped power bus bar assembly structure having integrated capacitors Grant 7,764,498 - Conn July 27, 2	2010-07-27
Stackable self-aligning insulative guide tray for holding semiconductor substrates Grant 7,719,844 - Conn May 18, 2	2010-05-18
Large substrate structural vias Grant 7,709,966 - Conn May 4, 2	2010-05-04
Flip-chip package having thermal expansion posts Grant 7,667,473 - Conn , et al. February 23, 2	2010-02-23
Through-substrate power-conducting via with embedded capacitance App 20090267183 - Temple; Dorota ; et al.	2009-10-29
Method and mechanism for controlling power consumption of an integrated circuit Grant 7,581,124 - Jacobson , et al. August 25, 2	2009-08-25
Interposing structure Grant 7,566,960 - Conn July 28, 2	2009-07-28
Disabling unused/inactive resources in programmable logic devices for static power reduction Grant 7,562,332 - Tuan , et al. July 14, 2	2009-07-14
Tuning programmable logic devices for low-power design implementation Grant 7,549,139 - Tuan , et al. June 16, 2	2009-06-16
Local defect memories on semiconductor substrates in a stack computer App 20090079463 - Conn; Robert O.	2009-03-26
Semiconductor substrate elastomeric stack App 20090079058 - Conn; Robert O.	2009-03-26
Integrated semiconductor substrate structure using incompatible processes App 20090079059 - Conn; Robert O.	2009-03-26
Comb-shaped power bus bar assembly structure having integrated capacitors App 20090080158 - Conn; Robert O.	2009-03-26
Stackable self-aligning insulative guide tray for holding semiconductor substrates App 20090080152 - Conn; Robert O.	2009-03-26
Large Substrate Structural Vias App 20090079056 - Conn; Robert O.	2009-03-26
Preventing breakage of long metal signal conductors on semiconductor substrates App 20090079084 - Conn; Robert O.	2009-03-26
Regulating unused/inactive resources in programmable logic devices for static power reduction Grant 7,504,854 - Look , et al. March 17, 2	2009-03-17
Self-heating mechanism for duplicating microbump failure conditions in FPGAs and for logging failures Grant 7,362,121 - Conn , et al. April 22, 2	2008-04-22
Remote field upgrading of programmable logic device configuration data via adapter connected to target memory socket Grant 7,269,724 - Trimberger , et al. September 11, 2	2007-09-11
Interposer for impedance matching Grant 7,233,061 - Conn June 19, 2	2007-06-19
Disabling unused/inactive resources in programmable logic devices for static power reduction Grant 7,098,689 - Tuan , et al. August 29, 2	2006-08-29
Shielded platform for die-bonding an analog die to an FPGA Grant 7,084,487 - Conn August 1, 2	2006-08-01
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit Grant 7,068,072 - New , et al. June 27, 2	2006-06-27
Bond and back side etchback transistor fabrication process Grant 7,064,391 - Conn June 20, 2	2006-06-20
Series capacitor coupling multiplexer for programmable logic devices Grant 7,046,071 - Conn , et al. May 16, 2	2006-05-16
Coaxial clock tree for programmable logic devices Grant 6,998,876 - Conn February 14, 2	2006-02-14
Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit Grant 6,961,231 - Alexander , et al. November 1, 2	2005-11-01
Fiber optic field programmable gate array integrated circuit packaging Grant 6,945,712 - Conn September 20, 2	2005-09-20
Optical testing port and wafer level testing without probe cards Grant 6,897,663 - Conn May 24, 2	2005-05-24
Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit Grant 6,891,258 - Alexander , et al. May 10, 2	2005-05-10
Tunable clock distribution system for reducing power dissipation Grant 6,882,182 - Conn , et al. April 19, 2	2005-04-19
Capacitive interposer Grant 6,875,921 - Conn April 5, 2	2005-04-05
Method to produce a factory programmable IC using standard IC wafers and the structure Grant 6,864,142 - Conn March 8, 2	2005-03-08
Semiconductor wafer with well contacts on back side Grant 6,864,156 - Conn March 8, 2	2005-03-08
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit App 20040268286 - New, Bernard J. ; et al.	2004-12-30
Optical testing port and wafer level testing without probe cards Grant 6,815,973 - Conn November 9, 2	2004-11-09
Fiber optic integrated circuit package using micromirrors Grant 6,789,959 - Conn September 14, 2	2004-09-14
Stacked dice bonded with aluminum posts Grant 6,756,305 - Conn June 29, 2	2004-06-29
Bond and back side etchback transistor fabrication process Grant 6,753,239 - Conn June 22, 2	2004-06-22
Built-in self test using pulse generators Grant 6,611,477 - Speyer , et al. August 26, 2	2003-08-26
Built-in AC self test using pulse generators Grant 6,466,520 - Speyer , et al. October 15, 2	2002-10-15
Built-in self test method for measuring clock to out delays Grant 6,356,514 - Wells , et al. March 12, 2	2002-03-12
Method and system for measuring signal propagation delays using ring oscillators Grant 6,219,305 - Patrie , et al. April 17, 2	2001-04-17
User-controlled delay circuit for a programmable logic device Grant 6,150,863 - Conn , et al. November 21, 2	2000-11-21
Variable-delay interconnect structure for a programmable logic device Grant 6,008,666 - Conn December 28, 1	1999-12-28
Method for characterizing interconnect timing characteristics Grant 6,005,829 - Conn December 21, 1	1999-12-21
Structure and method for reading blocks of data from selectable points in a memory device Grant 5,923,614 - Erickson , et al. July 13, 1	1999-07-13
Method for characterizing interconnect timing characteristics using reference ring oscillator circuit Grant 5,790,479 - Conn August 4, 1	1998-08-04
Structure and method for reading blocks of data from selectable points in a memory device Grant 5,789,938 - Erickson , et al. August 4, 1	1998-08-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.