Colburn; Matthew Earl
Patent Applications and Registrations
Patent applications and USPTO patent grants for Colburn; Matthew Earl.The latest application filed is for "interconnect structures with partially self aligned vias and methods to produce same".
- Colburn; Matthew Earl - Hopewell Junction NY
- Colburn; Matthew Earl - Schenectady NY
- Colburn; Matthew Earl - Waukesha WI
| Patent | Date |
|---|---|
| Electronics structures using a sacrificial multi-layer hardmask scheme Grant 7,947,907 - Colburn , et al. May 24, 2 | 2011-05-24 |
| Method to generate airgaps with a template first scheme and a self aligned blockout mask Grant 7,863,150 - Colburn , et al. January 4, 2 | 2011-01-04 |
| Interconnect Structures With Partially Self Aligned Vias And Methods To Produce Same App 20090200683 - Colburn; Matthew Earl ; et al. | 2009-08-13 |
| Method Of Forming A Dual-damascene Structure Using An Underlayer App 20090093114 - Burns; Sean David ; et al. | 2009-04-09 |
| Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme App 20080251284 - Colburn; Matthew Earl ; et al. | 2008-10-16 |
| Process for preparing electronics structures using a sacrificial multilayer hardmask scheme Grant 7,371,684 - Colburn , et al. May 13, 2 | 2008-05-13 |
| Line level air gaps App 20060264036 - Chen; Shyng-Tsong ; et al. | 2006-11-23 |
| Process for preparing electronics structures using a sacrificial multilayer hardmask scheme App 20060258159 - Colburn; Matthew Earl ; et al. | 2006-11-16 |
| Line level air gaps Grant 7,084,479 - Chen , et al. August 1, 2 | 2006-08-01 |
| Line level air gaps App 20050127514 - Chen, Shyng-Tsong ; et al. | 2005-06-16 |
| Step and flash imprint lithography Grant 6,719,915 - Willson , et al. April 13, 2 | 2004-04-13 |
| Step and flash imprint lithography Grant 6,334,960 - Willson , et al. January 1, 2 | 2002-01-01 |
| Step and flash imprint lithography App 20010040145 - Willson, Carlton Grant ; et al. | 2001-11-15 |
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