Col; Gerard M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Col; Gerard M..The latest application filed is for "mechanism to preclude load replays dependent on fuse array access in an out-of-order processor".

Company Profile

5.72.59

Col; Gerard M. - Austin TX
- Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for programmable load replay preclusion Grant 10,228,944 - Col , et al.	2019-03-12
Apparatus and method for programmable load replay preclusion Grant 10,209,996 - Col , et al. Feb	2019-02-19
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Grant 10,175,984 - Col , et al. J	2019-01-08
Load replay precluding mechanism Grant 10,146,539 - Col , et al. De	2018-12-04
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Grant 10,146,547 - Col , et al. De	2018-12-04
Load replay precluding mechanism Grant 10,146,546 - Col , et al. De	2018-12-04
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Grant 10,146,540 - Col , et al. De	2018-12-04
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor Grant 10,133,579 - Col , et al. November 20, 2	2018-11-20
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Grant 10,133,580 - Col , et al. November 20, 2	2018-11-20
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor Grant 10,127,046 - Col , et al. November 13, 2	2018-11-13
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Grant 10,120,689 - Col , et al. November 6, 2	2018-11-06
Programmable load replay precluding mechanism Grant 10,114,646 - Col , et al. October 30, 2	2018-10-30
Programmable load replay precluding mechanism Grant 10,114,794 - Col , et al. October 30, 2	2018-10-30
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Grant 10,108,430 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Grant 10,108,427 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Grant 10,108,420 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor Grant 10,108,429 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude shared ram-dependent load replays in an out-of-order processor Grant 10,108,421 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Grant 10,108,428 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude I/O-dependent load replays in an out-of-order processor Grant 10,095,514 - Col , et al. October 9, 2	2018-10-09
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Grant 10,089,112 - Col , et al. October 2, 2	2018-10-02
Mechanism to preclude I/O-dependent load replays in an out-of-order processor Grant 10,088,881 - Col , et al. October 2, 2	2018-10-02
Mechanism to preclude load replays dependent on page walks in an out-of-order processor Grant 10,083,038 - Col , et al. September 25, 2	2018-09-25
Microprocessor with ALU integrated into store unit Grant 9,952,875 - Col , et al. April 24, 2	2018-04-24
Power saving mechanism to reduce load replays in out-of-order processor Grant 9,915,998 - Col , et al. March 13, 2	2018-03-13
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor Grant 9,804,845 - Col , et al. October 31, 2	2017-10-31
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor Grant 9,740,271 - Col , et al. August 22, 2	2017-08-22
Power saving mechanism to reduce load replays in out-of-order processor Grant 9,703,359 - Col , et al. July 11, 2	2017-07-11
Conditional store instructions in an out-of-order execution microprocessor Grant 9,645,822 - Henry , et al. May 9, 2	2017-05-09
Mechanism to preclude load replays dependent on page walks in an out-of-order processor Grant 9,645,827 - Col , et al. May 9, 2	2017-05-09
Processor that leapfrogs MOV instructions Grant 9,588,769 - Col , et al. March 7, 2	2017-03-07
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor App 20160357568 - COL; GERARD M. ; et al.	2016-12-08
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor App 20160349825 - COL; Gerard M. ; et al.	2016-12-01
Apparatus And Method For Programmable Load Replay Preclusion App 20160350123 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor App 20160350126 - COL; GERARD M. ; et al.	2016-12-01
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor App 20160350121 - COL; GERARD M. ; et al.	2016-12-01
Load Replay Precluding Mechanism App 20160350119 - COL; GERARD M. ; et al.	2016-12-01
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor App 20160350122 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor App 20160350118 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor App 20160350120 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor App 20160350127 - COL; Gerard M. ; et al.	2016-12-01
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor App 20160342414 - COL; GERARD M. ; et al.	2016-11-24
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor App 20160342420 - COL; GERARD M. ; et al.	2016-11-24
Microprocessor with ALU integrated into load unit Grant 9,501,286 - Col , et al. November 22, 2	2016-11-22
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor App 20160209910 - COL; GERARD M. ; et al.	2016-07-21
Conditional load instructions in an out-of-order execution microprocessor Grant 9,378,019 - Henry , et al. June 28, 2	2016-06-28
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor App 20160170762 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor App 20160170753 - COL; GERARD M. ; et al.	2016-06-16
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor App 20160170758 - COL; GERARD M. ; et al.	2016-06-16
Programmable Load Replay Precluding Mechanism App 20160170757 - COL; GERARD M. ; et al.	2016-06-16
Programmable Load Replay Precluding Mechanism App 20160170766 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor App 20160170760 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor App 20160170755 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method For Programmable Load Replay Preclusion App 20160170764 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor App 20160170756 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor App 20160170751 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor App 20160170763 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor App 20160170752 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor App 20160170761 - COL; GERARD M. ; et al.	2016-06-16
Load Replay Precluding Mechanism App 20160170754 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor App 20160170759 - COL; GERARD M. ; et al.	2016-06-16
Microprocessor that translates conditional load/store instructions into variable number of microinstructions Grant 9,244,686 - Henry , et al. January 26, 2	2016-01-26
Processor That Leapfrogs Mov Instructions App 20150347140 - Col; Gerard M. ; et al.	2015-12-03
Efficient conditional ALU instruction in read-port limited register file microprocessor Grant 9,032,189 - Henry , et al. May 12, 2	2015-05-12
Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor Grant 8,924,695 - Henry , et al. December 30, 2	2014-12-30
Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor Grant 08924695 -	2014-12-30
Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction Grant 8,909,908 - Hooker , et al. December 9, 2	2014-12-09
Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor Grant 8,880,857 - Henry , et al. November 4, 2	2014-11-04
Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register Grant 8,880,854 - Hooker , et al. November 4, 2	2014-11-04
Microprocessor That Translates Conditional Load/store Instructions Into Variable Number Of Microinstructions App 20140122847 - Henry; G. Glenn ; et al.	2014-05-01
Conditional Store Instructions In An Out-of-order Execution Microprocessor App 20140122843 - Henry; G. Glenn ; et al.	2014-05-01
Conditional Load Instructions In An Out-of-order Execution Microprocessor App 20140013089 - Henry; G. Glenn ; et al.	2014-01-09
Apparatus and method for detection and correction of denormal speculative floating point operand Grant 8,495,343 - Henry , et al. July 23, 2	2013-07-23
Out-of-order X86 microprocessor with fast shift-by-zero handling Grant 8,332,618 - Col , et al. December 11, 2	2012-12-11
Conditional Alu Instruction Condition Satisfaction Propagation Between Microinstructions In Read-port Limited Register File Microprocessor App 20120260071 - Henry; G. Glenn ; et al.	2012-10-11
Efficient Conditional Alu Instruction In Read-port Limited Register File Microprocessor App 20120260074 - Henry; G. Glenn ; et al.	2012-10-11
Conditional Alu Instruction Pre-shift-generated Carry Flag Propagation Between Microinstructions In Read-port Limited Register File Microprocessor App 20120260075 - Henry; G. Glenn ; et al.	2012-10-11
Microprocessor with fused store address/store data microinstruction Grant 8,090,931 - Col , et al. January 3, 2	2012-01-03
Out-of-order execution microprocessor that selectively initiates instruction retirement early Grant 8,074,060 - Col , et al. December 6, 2	2011-12-06
Microprocessor with microinstruction-specifiable non-architectural condition code flag register Grant 8,069,339 - Henry , et al. November 29, 2	2011-11-29
Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions Grant 8,069,340 - Hooker , et al. November 29, 2	2011-11-29
Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture Grant 7,937,561 - Col , et al. May 3, 2	2011-05-03
Apparatus And Method For Detection And Correction Of Denormal Speculative Floating Point Operand App 20110060943 - Henry; G. Glenn ; et al.	2011-03-10
Microprocessor With Alu Integrated Into Store Unit App 20110035570 - Col; Gerard M. ; et al.	2011-02-10
Out-of-order X86 Microprocessor With Fast Shift-by-zero Handling App 20110035573 - Col; Gerard M. ; et al.	2011-02-10
Microprocessor With Alu Integrated Into Load Unit App 20110035569 - Col; Gerard M. ; et al.	2011-02-10
Microprocessor With Selective Out-of-order Branch Execution App 20100306506 - Hooker; Rodney E. ; et al.	2010-12-02
Microprocessor With Microinstruction-specifiable Non-architectural Condition Code Flag Register App 20100299504 - Henry; G. Glenn ; et al.	2010-11-25
Out-of-order Execution Microprocessor That Speculatively Executes Dependent Memory Access Instructions By Predicting No Value Change By Older Instructions That Load A Segment Register App 20100205406 - Hooker; Rodney E. ; et al.	2010-08-12
Out-of-order Execution Microprocessor That Selectively Initiates Instruction Retirement Early App 20100131742 - Col; Gerard M. ; et al.	2010-05-27
Microprocessor With Fused Store Address/store Data Microinstruction App 20100070741 - Col; Gerard M. ; et al.	2010-03-18
Merge Microinstruction For Minimizing Source Dependencies In Out-of-order Execution Microprocessor With Variable Data Size Macroarchitecture App 20090254735 - Col; Gerard M. ; et al.	2009-10-08
Microprocessor With Microarchitecture For Efficiently Executing Read/modify/write Memory Operand Instructions App 20090204800 - Hooker; Rodney E. ; et al.	2009-08-13
Pipelined microprocessor, apparatus, and method for generating early instruction results Grant 7,185,182 - Col February 27, 2	2007-02-27
Processor including fallback branch prediction mechanism for far jump and far call instructions Grant 7,117,347 - Col , et al. October 3, 2	2006-10-03
Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions Grant 7,107,438 - Col September 12, 2	2006-09-12
Pipelined microprocessor, apparatus, and method for generating early status flags Grant 7,100,024 - Col August 29, 2	2006-08-29
Apparatus and method for masked move to and from flags register in a processor Grant 7,076,639 - Col , et al. July 11, 2	2006-07-11
Apparatus and method for masked move to and from flags register in a processor Grant 7,058,794 - Col , et al. June 6, 2	2006-06-06
Paired load-branch operation for indirect near jumps Grant 7,055,022 - Col , et al. May 30, 2	2006-05-30
Microprocessor apparatus and method for accelerating execution of repeat string instructions Grant 7,039,793 - Col , et al. May 2, 2	2006-05-02
Apparatus and method for masked move to and from flags register in a processor App 20050262330 - Col, Gerard M. ; et al.	2005-11-24
Apparatus and method for masked move to and from flags register in a processor App 20050228974 - Col, Gerard M. ; et al.	2005-10-13
Processor including fallback branch prediction mechanism for far jump and far call instructions App 20050210224 - Col, Gerard M. ; et al.	2005-09-22
Pipelined microprocessor, apparatus, and method for generating early instruction results App 20050182918 - Col, Gerard M.	2005-08-18
Pop-compare micro instruction for repeat string operations Grant 6,931,517 - Col , et al. August 16, 2	2005-08-16
Pop-compare Micro Instruction For Repeat String Operations App 20050177705 - Col, Gerard M. ; et al.	2005-08-11
Processor with improved repeat string operations App 20050144426 - Col, Gerard M. ; et al.	2005-06-30
Processor including branch prediction mechanism for far jump and far call instructions App 20050144427 - Col, Gerard M. ; et al.	2005-06-30
Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions App 20040158697 - Col, Gerard M.	2004-08-12
Pipelined microprocessor, apparatus, and method for generating early status flags App 20040158696 - Col, Gerard M.	2004-08-12
Address stage logic for generating speculative address operand interim results of preceding instruction by arithmetic operations and configuring Grant 6,725,359 - Col April 20, 2	2004-04-20
Compare branch instruction pairing within a single integer pipeline Grant 6,647,489 - Col , et al. November 11, 2	2003-11-11
Arithmetic computation of potential addresses App 20030196073 - Col, Gerard M.	2003-10-16
Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction Grant 6,629,234 - Col September 30, 2	2003-09-30
Apparatus and method for improved non-page fault loads and stores Grant 6,581,150 - Col , et al. June 17, 2	2003-06-17
System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution Grant 6,349,383 - Col , et al. February 19, 2	2002-02-19
Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection Grant 6,189,091 - Col , et al. February 13, 2	2001-02-13