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Virtual memory address translation mechanism with controlled data persistence
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Memory controller for protected memory with automatic access granting capability
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Method for improving the efficiency of arithmetic code generation in an optimizing compiler using the technique of reassociation
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Virtual memory address translation mechanism with controlled data persistence
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Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system
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Condition register architecture for a primitive instruction set machine
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Grant 3,800,291 - Cocke , et al. March 26, 1 | 1974-03-26 |
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Method Of And Apparatus For Decoding Variable-length Codes Having Length-indicating Prefixes
Grant 3,701,111 - Cocke , et al. October 24, 1 | 1972-10-24 |
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Apparatus In A Digital Computer For Allowing The Skipping Of Predetermined Instructions In A Sequence Of Instructions, In Response To The Occurrence Of Certain Conditions
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