Cline; Roger A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cline; Roger A..The latest application filed is for "electrostatic discharge protection device for high voltage".

Company Profile

1.11.9

Cline; Roger A. - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrostatic discharge protection device for high voltage Grant 10,177,136 - Cline , et al. J	2019-01-08
Electrostatic Discharge Protection Device For High Voltage App 20170338222 - Cline; Roger A. ; et al.	2017-11-23
Electrostatic discharge protection device for high voltage Grant 9,768,159 - Cline , et al. September 19, 2	2017-09-19
Electrostatic Discharge Protection Device For High Voltage App 20170053905 - Cline; Roger A. ; et al.	2017-02-23
ESD protection using diode-isolated gate-grounded nMOS with diode string Grant 9,269,703 - Pok , et al. February 23, 2	2016-02-23
Esd Protection Using Diode-isolated Gate-grounded Nmos With Diode String App 20140342515 - POK; Ponnarith ; et al.	2014-11-20
ESD protection using diode-isolated gate-grounded NMOS with diode string Grant 8,829,618 - Pok , et al. September 9, 2	2014-09-09
Esd Protection Using Diode-isolated Gate-grounded Nmos With Diode String App 20120112286 - Pok; Ponnarith ; et al.	2012-05-10
Apparatus and method for electrostatic discharge protection with p-well integrated components App 20080277727 - Patel; Pravin P. ; et al.	2008-11-13
Design implementation to suppress latchup in voltage tolerant circuits Grant 7,167,350 - Salcedo-Suner , et al. January 23, 2	2007-01-23
ESD protection with uniform substrate bias Grant 6,900,969 - Salling , et al. May 31, 2	2005-05-31
Design implementation to suppress latchup in voltage tolerant circuits App 20050104154 - Salcedo-Suner, Jorge ; et al.	2005-05-19
Output buffer and I/O protection circuit for CMOS technology Grant 6,826,026 - Duvvury , et al. November 30, 2	2004-11-30
ESD protection with uniform substrate bias App 20040114287 - Salling, Craig T. ; et al.	2004-06-17
Output buffer and I/O protection circuit for CMOS technology App 20030048588 - Duvvury, Charvaka ; et al.	2003-03-13
Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process App 20020027755 - Andresen, Bernhard H. ; et al.	2002-03-07
NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors Grant 6,310,379 - Andresen , et al. October 30, 2	2001-10-30
CMOS triggered NMOS ESD protection circuit Grant 6,147,538 - Andresen , et al. November 14, 2	2000-11-14
Autoranging digital analog phase locked loop Grant 5,487,093 - Adresen , et al. January 23, 1	1996-01-23

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