Cline; Leslie E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cline; Leslie E..The latest application filed is for "intervention of independent self-regulation of power consumption devices".

Company Profile

0.24.22

Cline; Leslie E. - Sunnyvale CA
Cline, Leslie E - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Performance reduction limit for power consumption device Grant 9,170,626 - Cline , et al. October 27, 2	2015-10-27
Intervention Of Independent Self-regulation Of Power Consumption Devices App 20110127834 - Cline; Leslie E. ; et al.	2011-06-02
Intervention of independent self-regulation of power consumption devices Grant 7,884,499 - Cline , et al. February 8, 2	2011-02-08
Intervention Of Independent Self-regulation Of Power Consumption Devices App 20090322150 - Cline; Leslie E. ; et al.	2009-12-31
System And Method of Coherent Data Transfer During Processor Idle States App 20090193274 - Cline; Leslie E. ; et al.	2009-07-30
System and method of coherent data transfer during processor idle states Grant 7,523,327 - Cline , et al. April 21, 2	2009-04-21
Audio noise mitigation for power state transitions Grant 7,472,289 - Rodriguez , et al. December 30, 2	2008-12-30
Reducing storage data transfer interference with processor power management Grant 7,373,534 - Cline May 13, 2	2008-05-13
Method and apparatus for dynamic DLL powerdown and memory self-refresh Grant 7,343,502 - Samson , et al. March 11, 2	2008-03-11
USB schedule prefetcher for low power Grant 7,340,550 - Derr , et al. March 4, 2	2008-03-04
Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications Grant 7,281,074 - Diefenbaugh , et al. October 9, 2	2007-10-09
Future activity list for peripheral bus host controller Grant 7,231,468 - Cline June 12, 2	2007-06-12
Method and apparatus for enabling a low power mode for a processor Grant 7,225,347 - Dai , et al. May 29, 2	2007-05-29
Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications App 20070005859 - Diefenbaugh; Paul S. ; et al.	2007-01-04
Reducing storage data transfer interference with processor power management App 20060294406 - Cline; Leslie E.	2006-12-28
Power management for an integrated graphics device Grant 7,149,909 - Cui , et al. December 12, 2	2006-12-12
System and method of coherent data transfer during processor idle states App 20060200690 - Cline; Leslie E. ; et al.	2006-09-07
Method and apparatus for avoiding race condition with edge-triggered interrupts Grant 7,069,367 - Poisner , et al. June 27, 2	2006-06-27
Audio noise mitigation for power state transitions App 20060132109 - Rodriguez; Jorge P. ; et al.	2006-06-22
USB schedule prefetcher for low power App 20060123180 - Derr; Michael N. ; et al.	2006-06-08
Method and apparatus for enabling a low power mode for a processor App 20060095806 - Dai; Xia ; et al.	2006-05-04
Method and apparatus for dynamic DLL powerdown and memory self-refresh App 20060020835 - Samson; Eric C. ; et al.	2006-01-26
System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field Grant 6,988,211 - Cline , et al. January 17, 2	2006-01-17
Method and apparatus for enabling a low power mode for a processor Grant 6,976,181 - Dai , et al. December 13, 2	2005-12-13
Method and apparatus for logical detach for a hot-plug-in data bus Grant 6,871,252 - Cline March 22, 2	2005-03-22
Low pin count docking architecture for a trusted platform App 20050044408 - Bajikar, Sundeep M. ; et al.	2005-02-24
Future activity list for peripheral bus host controller App 20050033869 - Cline, Leslie E.	2005-02-10
Method and apparatus to directly access a peripheral device when central processor operations are suspended Grant 6,802,018 - Bormann , et al. October 5, 2	2004-10-05
Computer peripheral device that remains operable when central processor operations are suspended Grant 6,748,548 - Bormann , et al. June 8, 2	2004-06-08
Entering and exiting power managed states without disrupting accelerated graphics port transactions Grant 6,738,068 - Cohen , et al. May 18, 2	2004-05-18
Dynamically changing the performance of devices in a computer platform Grant 6,704,877 - Cline , et al. March 9, 2	2004-03-09
Entering and exiting power managed states without disrupting accelerated graphics port transactions App 20040032414 - Jain, Satchit ; et al.	2004-02-19
Power management for an integrated graphics device App 20030210247 - Cui, Ying ; et al.	2003-11-13
Method and apparatus for enabling a low power mode for a processor App 20030120962 - Dai, Xia ; et al.	2003-06-26
Method and apparatus to permit a peripheral device to become the default system bus master App 20020124125 - Bormann, David ; et al.	2002-09-05
Computer peripheral device that remains operable when central processor operations are suspended App 20020124198 - Bormann, David ; et al.	2002-09-05
Method and apparatus to directly access a peripheral device when central processor operations are suspended App 20020116554 - Bormann, David ; et al.	2002-08-22
Dynamically changing the performance of devices in a computer platform App 20020087897 - Cline, Leslie E. ; et al.	2002-07-04
Method and apparatus for avoiding race condition with edge-triggered interrupts App 20020087774 - Poisner, David I. ; et al.	2002-07-04
Entering and exiting power managed states without disrupting accelerated graphics port transactions App 20020085008 - Jain, Satchit ; et al.	2002-07-04
Processor performance state control App 20020087896 - Cline, Leslie E. ; et al.	2002-07-04
Method and apparatus for implementing a DMA timeout counter feature Grant 5,826,107 - Cline , et al. October 20, 1	1998-10-20
Translating from a PIO protocol to DMA protocol with a peripheral interface circuit Grant 5,630,171 - Chejlava, Jr. , et al. May 13, 1	1997-05-13
Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus Grant 5,603,052 - Chejlava, Jr. , et al. February 11, 1	1997-02-11
Interface circuit for transferring data between host device and mass storage device in response to designated address in host memory space assigned as data port Grant 5,592,682 - Chejlava, Jr. , et al. January 7, 1	1997-01-07

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