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Bitcell Architecture
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TSV Coupled Integrated Circuits and Methods
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Dielet design techniques
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Optical Waveguide Connecting Device
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Wirelength distribution schemes and techniques
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Multi-tier co-placement for integrated circuitry
Grant 11,120,191 - Xu , et al. September 14, 2 | 2021-09-14 |
Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array
Grant 11,004,479 - Bhargava , et al. May 11, 2 | 2021-05-11 |
Dielet Design Techniques
App 20210081508 - Xu; Xiaoqing ; et al. | 2021-03-18 |
Spiking neural network
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Systems, devices, and/or processes for OMIC content processing and/or communication
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Systems, devices, and/or processes for omic content processing and/or partitioning
Grant 10,841,299 - St Amant , et al. November 17, 2 | 2020-11-17 |
Computer implemented system and method for generating a layout of a cell defining a circuit component
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Wirelength Distribution Schemes and Techniques
App 20200279067 - Prasad; Divya Madapusi Srinivas ; et al. | 2020-09-03 |
Method And Apparatus For Generating Three-dimensional Integrated Circuit Design
App 20200257841 - A1 | 2020-08-13 |
Method, system and device for integration of volatile and non-volatile memory bitcells
Grant 10,741,246 - Bhargava , et al. A | 2020-08-11 |
Method, System And Device For Integration Of Bitcells In A Volatile Memory Array And Bitcells In A Non-volatile Memory Array
App 20200251152 - Kind Code | 2020-08-06 |
Multi-Tier Co-Placement for Integrated Circuitry
App 20200218845 - Xu; Xiaoqing ; et al. | 2020-07-09 |
Method for generating three-dimensional integrated circuit design
Grant 10,678,985 - Sinha , et al. | 2020-06-09 |
Wirelength distribution schemes and techniques
Grant 10,657,218 - Prasad , et al. | 2020-05-19 |
Optical waveguide connecting device
Grant 10,641,953 - Vashishtha , et al. | 2020-05-05 |
Optical Waveguide Connecting Device
App 20200132929 - Vashishtha; Vinay ; et al. | 2020-04-30 |
Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array
Grant 10,607,659 - Bhargava , et al. | 2020-03-31 |
Multi-tier co-placement for integrated circuitry
Grant 10,599,806 - Xu , et al. | 2020-03-24 |
Method, System And Device For Integration Of Volatile And Non-volatile Memory Bitcells
App 20190325959 - Bhargava; Mudit ; et al. | 2019-10-24 |
Method, System And Device For Integration Of Bitcells In A Volatile Memory Array And Bitcells In A Non-volatile Memory Array
App 20190325919 - Bhargava; Mudit ; et al. | 2019-10-24 |
Multi-Tier Co-Placement for Integrated Circuitry
App 20190303523 - Xu; Xiaoqing ; et al. | 2019-10-03 |
Systems, Devices, And/or Processes For Omic Content Processing And/or Partitioning
App 20190288999 - St Amant; Renee Marie ; et al. | 2019-09-19 |
Systems, Devices, And/or Processes For Omic Content Processing And/or Communication
App 20190288837 - St Amant; Renee Marie ; et al. | 2019-09-19 |
Systems, Devices, And/or Processes For Omic And/or Behavioral Content Processing
App 20190286789 - St Amant; Renee Marie ; et al. | 2019-09-19 |
Systems, Devices, And/or Processes For Omic And/or Environmental Content Processing And/or Communication
App 20190287658 - St Amant; Renee Marie ; et al. | 2019-09-19 |
Circuit and method for configurable impedance array
Grant 10,381,076 - Bhavnagarwala , et al. A | 2019-08-13 |
Wirelength Distribution Schemes and Techniques
App 20190163860 - Prasad; Divya Madapusi Srinivas ; et al. | 2019-05-30 |
Computer Implemented System and Method for Generating a Layout of a Cell Defining a Circuit Component
App 20190026417 - de Dood; Paul ; et al. | 2019-01-24 |
Computer implemented system and method for generating a layout of a cell defining a circuit component
Grant 10,083,269 - De Dood , et al. September 25, 2 | 2018-09-25 |
Spiking Neural Network
App 20180260696 - SUDA; Naveen ; et al. | 2018-09-13 |
Computer Implemented System And Method For Generating A Layout Of A Cell Defining A Circuit Component
App 20180225402 - DE DOOD; Paul ; et al. | 2018-08-09 |
Circuit And Method For Configurable Impedance Array
App 20180218772 - Bhavnagarwala; Azeez Jennudin ; et al. | 2018-08-02 |
System and method for perforating redundant metal in self-aligned multiple patterning
Grant 10,002,222 - Cline , et al. June 19, 2 | 2018-06-19 |
Using inter-tier vias in integrated circuits
Grant 9,929,149 - Sinha , et al. March 27, 2 | 2018-03-27 |
Method For Generating Three-dimensional Integrated Circuit Design
App 20180060475 - SINHA; Saurabh Pijuskumar ; et al. | 2018-03-01 |
Circuit and method for configurable impedance array
Grant 9,905,295 - Bhavnagarwala , et al. February 27, 2 | 2018-02-27 |
System and Method for Perforating Redundant Metal in Self-Aligned Multiple Patterning
App 20180018420 - Cline; Brian Tracy ; et al. | 2018-01-18 |
Using Inter-Tier Vias in Integrated Circuits
App 20170365600 - Sinha; Saurabh Pijuskumar ; et al. | 2017-12-21 |
Circuit and method for configurable impedance array
Grant 9,773,550 - Bhavnagarwala , et al. September 26, 2 | 2017-09-26 |
Circuit And Method For Configurable Impedance Array
App 20170206963 - Bhavnagarwala; Azeez Jennudin ; et al. | 2017-07-20 |
Circuit And Method For Configurable Impedance Array
App 20170178724 - Bhavnagarwala; Azeez Jennudin ; et al. | 2017-06-22 |
Measurement circuitry and method for measuring a clock node to output node delay of a flip-flop
Grant 9,638,752 - Kim , et al. May 2, 2 | 2017-05-02 |
Measurement Circuitry And Method For Measuring A Clock Node To Output Node Delay Of A Flip-flop
App 20150226800 - KIM; Yejoong ; et al. | 2015-08-13 |
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