Ciraula; Michael K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ciraula; Michael K..The latest application filed is for "configuration of multi-die modules with through-silicon vias".

Company Profile

8.15.6

Ciraula; Michael K. - Fort Collins CO
Ciraula; Michael K. - Round Rock TX
Ciraula; Michael K. - Austin TX
Ciraula; Michael K. - Manassas VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Staged bitline precharge Grant 11,361,819 - Robison , et al. June 14, 2	2022-06-14
Flexibile interfaces using through-silicon via technology Grant 10,644,826 - Wuu , et al.	2020-05-05
Configuration of multi-die modules with through-silicon vias Grant 10,509,752 - Schreiber , et al. Dec	2019-12-17
Configuration Of Multi-die Modules With Through-silicon Vias App 20190332561 - Schreiber; Russell ; et al.	2019-10-31
Error injection for assessment of error detection and correction techniques using error injection logic and non-volatile memory Grant 10,452,505 - Ciraula Oc	2019-10-22
Flexibile Interfaces Using Through-silicon Via Technology App 20190268086 - Wuu; John ; et al.	2019-08-29
Staged Bitline Precharge App 20190189196 - ROBISON; Andrew ; et al.	2019-06-20
Error Injection For Assessment Of Error Detection And Correction Techniques Using Error Injection Logic And Non-volatile Memory App 20190188064 - CIRAULA; Michael K.	2019-06-20
Swizzling in 3D stacked memory Grant 10,303,398 - Wuu , et al.	2019-05-28
Swizzling In 3d Stacked Memory App 20190129651 - WUU; John ; et al.	2019-05-02
Predictive multistage comparison for associative memory Grant 9,916,246 - Henrion , et al. March 13, 2	2018-03-13
Predictive Multistage Comparison For Associative Memory App 20180052770 - Henrion; Carson Donahue ; et al.	2018-02-22
Wafer stage storage structure speed testing Grant 7,417,449 - Posey , et al. August 26, 2	2008-08-26
Memory array with global bitline domino read/write scheme Grant 7,355,881 - Dankert , et al. April 8, 2	2008-04-08
Decode structure with parallel rotation Grant 7,268,591 - Huber , et al. September 11, 2	2007-09-11
Circular buffer using age vectors Grant 7,080,170 - Zuraski, Jr. , et al. July 18, 2	2006-07-18
Circular buffer using grouping for find first function Grant 6,873,184 - McMinn , et al. March 29, 2	2005-03-29
Method and apparatus for synchronized pipeline data access of a memory system Grant 5,615,168 - Lattimore , et al. March 25, 1	1997-03-25
Extended segmented precharge architecture Grant 5,592,426 - Jallice , et al. January 7, 1	1997-01-07
Address transition detection (ATD) circuit for asynchronous VLSI chips Grant 5,566,130 - Durham , et al. October 15, 1	1996-10-15
Zero standby power, radiation hardened, memory redundancy circuit Grant 4,996,670 - Ciraula , et al. February 26, 1	1991-02-26

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