| Patent | Date |
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Methods for performing a non-contact electrical measurement on a cell, chip, wafer, die, or logic block
Grant 11,340,293 - De , et al. May 24, 2 | 2022-05-24 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,107,804 - Lam , et al. August 31, 2 | 2021-08-31 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,081,476 - Lam , et al. August 3, 2 | 2021-08-03 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,081,477 - Lam , et al. August 3, 2 | 2021-08-03 |
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Grant 11,075,194 - Lam , et al. July 27, 2 | 2021-07-27 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,018,126 - Lam , et al. May 25, 2 | 2021-05-25 |
Collaborative Learning Model for Semiconductor Applications
App 20210142122 - Honda; Tomonori ; et al. | 2021-05-13 |
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Grant 10,978,438 - Lam , et al. April 13, 2 | 2021-04-13 |
Systems, Devices, And Methods For Performing A Non-contact Electrical Measurement On A Cell, Non-contact Electrical Measurement Cell Vehicle, Chip, Wafer, Die, Or Logic Block
App 20210096179 - DE; Indranil ; et al. | 2021-04-01 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with res
Grant 10,854,522 - Lam , et al. December 1, 2 | 2020-12-01 |
IC with test structures embedded within a contiguous standard cell area
Grant 10,777,472 - Lam , et al. Sept | 2020-09-15 |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
Grant 10,593,604 - Lam , et al. | 2020-03-17 |
Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-t
Grant 10,290,552 - Lam , et al. | 2019-05-14 |
Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
Grant 10,269,786 - Lam , et al. | 2019-04-23 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated wit
Grant 10,211,111 - Lam , et al. Feb | 2019-02-19 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associat
Grant 10,211,112 - Lam , et al. Feb | 2019-02-19 |
Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for m
Grant 10,199,283 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated wi
Grant 10,199,284 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with re
Grant 10,199,288 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated w
Grant 10,199,293 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-
Grant 10,199,294 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip
Grant 10,199,290 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respect
Grant 10,199,289 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with r
Grant 10,199,286 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with re
Grant 10,199,287 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas
Grant 10,199,285 - Lam , et al. Fe | 2019-02-05 |
Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 10,109,539 - Lam , et al. October 23, 2 | 2018-10-23 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 10,096,530 - Lam , et al. October 9, 2 | 2018-10-09 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 10,096,529 - Lam , et al. October 9, 2 | 2018-10-09 |
Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells
Grant 9,984,944 - Lam , et al. May 29, 2 | 2018-05-29 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens
Grant 9,953,889 - Lam , et al. April 24, 2 | 2018-04-24 |
Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,947,601 - Lam , et al. April 17, 2 | 2018-04-17 |
Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,929,063 - Lam , et al. March 27, 2 | 2018-03-27 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,929,136 - Lam , et al. March 27, 2 | 2018-03-27 |
Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,922,890 - Lam , et al. March 20, 2 | 2018-03-20 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,922,968 - Lam , et al. March 20, 2 | 2018-03-20 |
Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,911,668 - Lam , et al. March 6, 2 | 2018-03-06 |
Process for making and using mesh-style NCEM pads
Grant 9,911,649 - Lam , et al. March 6, 2 | 2018-03-06 |
Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,911,669 - Lam , et al. March 6, 2 | 2018-03-06 |
Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate
Grant 9,911,670 - Lam , et al. March 6, 2 | 2018-03-06 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens
Grant 9,905,487 - Lam , et al. February 27, 2 | 2018-02-27 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
Grant 9,905,553 - Lam , et al. February 27, 2 | 2018-02-27 |
Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,899,276 - Lam , et al. February 20, 2 | 2018-02-20 |
Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,881,843 - Lam , et al. January 30, 2 | 2018-01-30 |
Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens
Grant 9,870,966 - Lam , et al. January 16, 2 | 2018-01-16 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,871,028 - Lam , et al. January 16, 2 | 2018-01-16 |
Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,870,962 - Lam , et al. January 16, 2 | 2018-01-16 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 9,865,583 - Lam , et al. January 9, 2 | 2018-01-09 |
Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Grant 9,831,141 - Lam , et al. November 28, 2 | 2017-11-28 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,825,018 - Lam , et al. November 21, 2 | 2017-11-21 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells
Grant 9,818,738 - Lam , et al. November 14, 2 | 2017-11-14 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,818,660 - Lam , et al. November 14, 2 | 2017-11-14 |
Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
Grant 9,805,994 - Lam , et al. October 31, 2 | 2017-10-31 |
Integrated circuit containing DOEs of NCEM-enabled fill cells
Grant 9,799,575 - Lam , et al. October 24, 2 | 2017-10-24 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
Grant 9,799,640 - Lam , et al. October 24, 2 | 2017-10-24 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least Via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured NCEM-enabled fill cells
Grant 9,793,253 - Lam , et al. October 17, 2 | 2017-10-17 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,786,650 - Lam , et al. October 10, 2 | 2017-10-10 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens
Grant 9,785,496 - Lam , et al. October 10, 2 | 2017-10-10 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,786,648 - Lam , et al. October 10, 2 | 2017-10-10 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 9,786,649 - Lam , et al. October 10, 2 | 2017-10-10 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, TS-short-configured, metal-short configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,780,083 - Lam , et al. October 3, 2 | 2017-10-03 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,778,974 - Lam , et al. October 3, 2 | 2017-10-03 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
Grant 9,773,775 - Lam , et al. September 26, 2 | 2017-09-26 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells
Grant 9,773,773 - Lam , et al. September 26, 2 | 2017-09-26 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
Grant 9,773,774 - Lam , et al. September 26, 2 | 2017-09-26 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,766,970 - Lam , et al. September 19, 2 | 2017-09-19 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
Grant 9,768,083 - Lam , et al. September 19, 2 | 2017-09-19 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,768,156 - Lam , et al. September 19, 2 | 2017-09-19 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATECNT-short-configured, metal-short-configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,761,574 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,761,573 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells
Grant 9,761,502 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,761,575 - Lam , et al. September 12, 2 | 2017-09-12 |
Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
Grant 9,748,153 - Lam , et al. August 29, 2 | 2017-08-29 |
Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells
Grant 9,741,703 - Lam , et al. August 22, 2 | 2017-08-22 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enables fill cells
Grant 9,741,741 - Lam , et al. August 22, 2 | 2017-08-22 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,728,553 - Lam , et al. August 8, 2 | 2017-08-08 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells
Grant 9,721,938 - Lam , et al. August 1, 2 | 2017-08-01 |
Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells
Grant 9,721,937 - Lam , et al. August 1, 2 | 2017-08-01 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells
Grant 9,711,496 - Lam , et al. July 18, 2 | 2017-07-18 |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Grant 9,711,421 - Lam , et al. July 18, 2 | 2017-07-18 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
Grant 9,691,672 - Lam , et al. June 27, 2 | 2017-06-27 |
Integrated Circuit Containing DOEs of NCEM-enabled Fill Cells
App 20170178981 - Lam; Stephen ; et al. | 2017-06-22 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,653,446 - Lam , et al. May 16, 2 | 2017-05-16 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells
Grant 9,646,961 - Lam , et al. May 9, 2 | 2017-05-09 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,627,371 - Lam , et al. April 18, 2 | 2017-04-18 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,627,370 - Lam , et al. April 18, 2 | 2017-04-18 |
Generalization of the photo process window and its application to OPC test pattern design
Grant 7,568,180 - Eisenmann , et al. July 28, 2 | 2009-07-28 |
Fast localization of electrical failures on an integrated circuit system and method
Grant 7,527,987 - Ciplickas , et al. May 5, 2 | 2009-05-05 |
Designing an integrated circuit to improve yield using a variant design element
Grant 7,487,474 - Ciplickas , et al. February 3, 2 | 2009-02-03 |
Generalization of the Photo Process Window and Its Application to Opc Test Pattern Design
App 20080295061 - Eisenmann; Hans ; et al. | 2008-11-27 |
Method for improving mask layout and fabrication
Grant 7,434,197 - Dolainsky , et al. October 7, 2 | 2008-10-07 |
Fast localization of electrical failures on an integrated circuit system and method
App 20060105475 - Ciplickas; Dennis ; et al. | 2006-05-18 |
Yield improvement
App 20060101355 - Ciplickas; Dennis ; et al. | 2006-05-11 |
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