Chung; Henry Wei-Ming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chung; Henry Wei-Ming.The latest application filed is for "mos transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture".

Company Profile

0.15.12

Chung; Henry Wei-Ming - Hsinchu TW
Chung; Henry Wei-Ming - Taipei TW
Chung; Henry Wei-Ming - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
MOS transistors having low-resistance salicide gates and a self-aligned contact between them Grant 7,605,414 - Chung October 20, 2	2009-10-20
MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture Grant 7,541,271 - Chung June 2, 2	2009-06-02
Method for reducing dimensions between patterns on a hardmask Grant 7,361,604 - Chung , et al. April 22, 2	2008-04-22
Method for reducing dimensions between patterns on a photoresist Grant 7,303,995 - Chung , et al. December 4, 2	2007-12-04
MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture App 20070207602 - Chung; Henry Wei-Ming	2007-09-06
MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture App 20060163667 - Chung; Henry Wei-Ming	2006-07-27
Method for reducing dimensions between patterns on a photoresist Grant 7,033,948 - Chung , et al. April 25, 2	2006-04-25
Method of fabricating phase shift mask Grant 6,887,627 - Chung , et al. May 3, 2	2005-05-03
Dual salicides for integrated circuits Grant 6,809,018 - Chung October 26, 2	2004-10-26
Method for reducing dimensions between patterns on a photoresist App 20040132225 - Chung, Henry Wei-Ming ; et al.	2004-07-08
Method for reducing dimensions between patterns on a photoresist Grant 6,750,150 - Chung , et al. June 15, 2	2004-06-15
Method for manufacturing an array structure in integrated circuits Grant 6,709,923 - Chung March 23, 2	2004-03-23
Method and structure of interconnection with anti-reflection coating App 20040018697 - Chung, Henry Wei-Ming	2004-01-29
Dual salicides for integrated circuits App 20040009652 - Chung, Henry Wei-Ming	2004-01-15
Method For Manufacturing An Array Structure In Integrated Circuits App 20030235950 - Chung, Henry Wei-Ming	2003-12-25
Method for reducing dimensions between patterns on a photomask App 20030224254 - Chung, Henry Wei-Ming ; et al.	2003-12-04
Method for reducing dimensions between patterns on a hardmask App 20030224602 - Chung, Henry Wei-Ming ; et al.	2003-12-04
Method for reducing dimensions between patterns on a photoresist App 20030216051 - Chung, Henry Wei-Ming ; et al.	2003-11-20
Method of fabricating phase shift mask App 20030203285 - Chung, Henry Wei-Ming ; et al.	2003-10-30
Method for reducing dimensions between patterns on a photoresist App 20030082916 - Chung, Henry Wei-Ming ; et al.	2003-05-01
Advanced interconnection for integrated circuits App 20020151165 - Chung, Henry Wei-Ming	2002-10-17
Interconnect structures for integrated circuits Grant 5,798,299 - Chung August 25, 1	1998-08-25
Method for forming a layer of metal silicide over the gates of a surface-channel CMOS device Grant 5,759,886 - Chung June 2, 1	1998-06-02
Integrated circuits with borderless vias Grant 5,757,077 - Chung , et al. May 26, 1	1998-05-26
Interconnect structures for integrated circuits Grant 5,666,007 - Chung September 9, 1	1997-09-09
Fabrication of integrated circuits with borderless vias Grant 5,656,543 - Chung August 12, 1	1997-08-12
Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region Grant 5,646,070 - Chung July 8, 1	1997-07-08

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