Chung; Chiu-Hua

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chung; Chiu-Hua.The latest application filed is for "shielding structure for ultra-high voltage semiconductor devices".

Company Profile

11.10.14

Chung; Chiu-Hua - Hsinchu TW
CHUNG; Chiu-Hua - Hsinchu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Pellicle frame with stress relief trenches Grant 11,415,878 - Lee , et al. August 16, 2	2022-08-16
Shielding Structure For Ultra-high Voltage Semiconductor Devices App 20220231133 - CHIU; Yi-Cheng ; et al.	2022-07-21
Pellicle Frame With Stress Relief Trenches App 20220082931 - LEE; Kuo-Hao ; et al.	2022-03-17
Semiconductor Device And Manufacturing Method Thereof App 20220069123 - Chiu; Yi-Cheng ; et al.	2022-03-03
Semiconductor Device Including A Capacitor App 20220028967 - CHEN; Hong-Yang ; et al.	2022-01-27
Semiconductor device including a capacitor Grant 11,145,709 - Chen , et al. October 12, 2	2021-10-12
Structure And Formation Method Of Semiconductor Device With Capacitors App 20210313416 - Luo; Guo-Jyun ; et al.	2021-10-07
Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device Grant 10,879,236 - Murukesan , et al. December 29, 2	2020-12-29
Method and system for aligning probe card in semiconductor device testing Grant 10,866,276 - Chuang , et al. December 15, 2	2020-12-15
Structure And Formation Method Of Semiconductor Device With Capacitors App 20200373380 - Luo; Guo-Jyun ; et al.	2020-11-26
Structure and formation method of semiconductor device with capacitors Grant 10,748,986 - Luo , et al. A	2020-08-18
Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device Grant 10,679,987 - Murukesan , et al.	2020-06-09
Method And System For Aligning Probe Card In Semiconductor Device Testing App 20200110131 - CHUANG; Kai-Di ; et al.	2020-04-09
Semiconductor Device Including A Capacitor App 20200105864 - CHEN; Hong-Yang ; et al.	2020-04-02
Bootstrap Metal-oxide-semiconductor (mos) Device Integrated With A High Voltage Mos (hvmos) Device And A High Voltage Junction T App 20200058647 - Murukesan; Karthick ; et al.	2020-02-20
Method and system for aligning probe card in semiconductor device testing Grant 10,509,071 - Chuang , et al. Dec	2019-12-17
Structure And Formation Method Of Semiconductor Device With Capacitors App 20190157378 - LUO; Guo-Jyun ; et al.	2019-05-23
Bootstrap Metal-oxide-semiconductor (mos) Device Integrated With A High Voltage Mos (hvmos) Device And A High Voltage Junction Termination (hvjt) Device App 20190131296 - Murukesan; Karthick ; et al.	2019-05-02
Method And System For Aligning Probe Card In Semiconductor Device Testing App 20180143244 - CHUANG; Kai-Di ; et al.	2018-05-24
High voltage semiconductor device Grant 9,680,009 - Murukesan , et al. June 13, 2	2017-06-13
High Voltage Semiconductor Device App 20170125582 - MURUKESAN; KARTHICK ; et al.	2017-05-04
Semiconductor structure and manufacturing method thereof Grant 9,331,081 - Lin , et al. May 3, 2	2016-05-03
Semiconductor Structure And Manufacturing Method Thereof App 20150115367 - LIN; CHUN-MING ; et al.	2015-04-30
Method of verifying a mask for a mask ROM Grant 6,773,937 - Ho , et al. August 10, 2	2004-08-10

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