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Patent applications and USPTO patent grants for Chung; Ching Thiam.The latest application filed is for "method to monitor critical dimension of ic interconnect".
Patent | Date |
---|---|
Method to monitor critical dimension of IC interconnect Grant 7,376,920 - Qian , et al. May 20, 2 | 2008-05-20 |
Method to monitor critical dimension of IC interconnect App 20070247167 - Qian; Hua ;   et al. | 2007-10-25 |
Method of wafer marking for multi-layer metal processes Grant 6,743,694 - Chung , et al. June 1, 2 | 2004-06-01 |
Method of self-aligning a damascene gate structure to isolation regions Grant 6,713,335 - Yen , et al. March 30, 2 | 2004-03-30 |
Method Of Self-aligning A Damascene Gate Structure To Isolation Regions App 20040038466 - Yen, Daniel ;   et al. | 2004-02-26 |
Method of wafer marking for multi-layer metal processes App 20030203589 - Chung, Ching Thiam ;   et al. | 2003-10-30 |
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