Chuang; Hak-Lay

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chuang; Hak-Lay.The latest application filed is for "n/p boundary effect reduction for metal gate transistors".

Company Profile

0.37.29

Chuang; Hak-Lay - Singapore N/A SG
Chuang; Hak-Lay - Hsinchu N/A TW
Chuang; Hak-Lay - US
Chuang; Hak-Lay - Hsinchu City TW
Chuang; Hak-Lay - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device for high-K and metal gate stacks Grant 9,711,415 - Lin , et al. July 18, 2	2017-07-18
N/P boundary effect reduction for metal gate transistors Grant 9,536,867 - Chuang , et al. January 3, 2	2017-01-03
System and method for a field-effect transistor with a raised drain structure Grant 9,257,347 - Chuang , et al. February 9, 2	2016-02-09
N/p Boundary Effect Reduction For Metal Gate Transistors App 20150364459 - Chuang; Hak-Lay ; et al.	2015-12-17
Method of fabricating a metal gate semiconductor device Grant 9,209,089 - Chung , et al. December 8, 2	2015-12-08
Enhanced gate replacement process for high-K metal gate technology Grant 9,177,870 - Chuang , et al. November 3, 2	2015-11-03
N/P boundary effect reduction for metal gate transistors Grant 9,123,694 - Chuang , et al. September 1, 2	2015-09-01
Method of hybrid high-k/metal-gate stack fabrication Grant 9,093,559 - Ng , et al. July 28, 2	2015-07-28
Self-aligned insulated film for high-k metal gate device Grant 8,822,283 - Ng , et al. September 2, 2	2014-09-02
Metal gate semiconductor device and method of fabricating thereof Grant 8,772,114 - Chuang , et al. July 8, 2	2014-07-08
Cost-effective gate replacement process Grant 8,753,931 - Zhu , et al. June 17, 2	2014-06-17
Device with a vertical gate structure Grant 8,742,492 - Chuang , et al. June 3, 2	2014-06-03
N/P boundary effect reduction for metal gate transistors Grant 8,703,595 - Chuang , et al. April 22, 2	2014-04-22
Device for high-K and metal gate stacks Grant 8,698,252 - Chen , et al. April 15, 2	2014-04-15
Semiconductor structure with suppressed STI dishing effect at resistor region Grant 8,691,673 - Chuang , et al. April 8, 2	2014-04-08
System And Method For A Field-effect Transistor With A Raised Drain Structure App 20140061775 - Chuang; Hak-Lay ; et al.	2014-03-06
Device with a Vertical Gate Structure App 20140042524 - Chuang; Hak-Lay ; et al.	2014-02-13
Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures Grant 8,635,573 - Chuang , et al. January 21, 2	2014-01-21
Large dimension device and method of manufacturing same in gate last process Grant 8,592,945 - Chuang , et al. November 26, 2	2013-11-26
Device And Methods For High-k And Metal Gate Stacks App 20130299913 - Lin; Jyun-Ming ; et al.	2013-11-14
Device And Methods For High-k And Metal Gate Stacks App 20130285150 - Chen; Po-Nien ; et al.	2013-10-31
Cost-Effective Gate Replacement Process App 20130264652 - Zhu; Ming ; et al.	2013-10-10
Metal Gate Semiconductor Device And Method Of Fabricating Thereof App 20130256805 - Chuang; Hak-Lay ; et al.	2013-10-03
Method Of Fabricating A Metal Gate Semiconductor Device App 20130260547 - Chung; Sheng-Chen ; et al.	2013-10-03
Contact for high-K metal gate device Grant 8,546,227 - Chuang , et al. October 1, 2	2013-10-01
Method Of Hybrid High-k/metal-gate Stack Fabrication App 20130234254 - Ng; Jin-Aun ; et al.	2013-09-12
Method of fabricating a dummy gate structure in a gate last process Grant 8,530,326 - Lai , et al. September 10, 2	2013-09-10
Enhanced Gate Replacement Process For High-k Metal Gate Technology App 20130154021 - Chuang; Hak-Lay ; et al.	2013-06-20
N/p Boundary Effect Reduction For Metal Gate Transistors App 20130126977 - Chuang; Hak-Lay ; et al.	2013-05-23
Contact For High-k Metal Gate Device App 20130069174 - Chuang; Hak-Lay ; et al.	2013-03-21
Self-aligned Insulated Film For High-k Metal Gate Device App 20130056837 - Ng; Jin-Aun ; et al.	2013-03-07
Integrated Circuit Device Having Defined Gate Spacing And Method Of Designing And Fabricating Thereof App 20130032884 - Chuang; Hak-Lay ; et al.	2013-02-07
Large Dimension Device and Method of Manufacturing Same in Gate Last Process App 20120319238 - Chuang; Hak-Lay ; et al.	2012-12-20
Semiconductor Structure With Suppressed Sti Dishing Effect At Resistor Region App 20120299115 - Chuang; Hak-Lay ; et al.	2012-11-29
Method of forming an interconnect structure with a graded composition using a nitrided target Grant 6,028,003 - Frisa , et al. February 22, 2	2000-02-22
Process for fabricating a semiconductor device Grant 5,961,791 - Frisa , et al. October 5, 1	1999-10-05
Lithographic proximity correction through subset feature modification Grant 5,958,635 - Reich , et al. September 28, 1	1999-09-28

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