CHU; Shao-Fu Sanford

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHU; Shao-Fu Sanford.The latest application filed is for "novel through silicon contact structure and method of forming the same".

Company Profile

1.29.26

CHU; Shao-Fu Sanford - Wuhan CN
Chu; Shao-Fu Sanford - Poughkeepsie NY
Chu; Shao-fu Sanford - Singapore SG
Chu; Shao-Fu Sanford - Dutchess County NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Novel Through Silicon Contact Structure And Method Of Forming The Same App 20210313251 - CHEN; Liang ; et al.	2021-10-07
Novel Through Silicon Contact Structure And Method Of Forming The Same App 20210296210 - CHEN; Liang ; et al.	2021-09-23
Through silicon contact structure and method of forming the same Grant 11,069,596 - Chen , et al. July 20, 2	2021-07-20
Staircase structures for three-dimensional memory device double-sided routing Grant 10,847,534 - Chu November 24, 2	2020-11-24
Novel Through Silicon Contact Structure And Method Of Forming The Same App 20200266128 - CHEN; Liang ; et al.	2020-08-20
Staircase Structures For Three-dimensional Memory Device Double-sided Routing App 20200006377 - Chu; Shao-Fu Sanford	2020-01-02
Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics Grant 9,466,661 - Triyoso , et al. October 11, 2	2016-10-11
Method Of Fabricating A Mim Capacitor With Minimal Voltage Coefficient And A Decoupling Mim Capacitor And Analog/rf Mim Capacitor On The Same Chip With High-k Dielectrics App 20160104762 - TRIYOSO; Dina ; et al.	2016-04-14
Integrated circuit system with double doped drain transistor Grant 9,269,770 - Li , et al. February 23, 2	2016-02-23
Integrated circuit system with hierarchical capacitor and method of manufacture thereof Grant 8,536,016 - Chu , et al. September 17, 2	2013-09-17
Integrated circuit system with high voltage transistor and method of manufacture thereof Grant 8,138,051 - Dong , et al. March 20, 2	2012-03-20
Integrated circuit system employing back end of line via techniques Grant 8,115,276 - Zhang , et al. February 14, 2	2012-02-14
Integrated Circuit System With Hierarchical Capacitor And Method Of Manufacture Thereof App 20120007214 - Chu; Shao-fu Sanford ; et al.	2012-01-12
Integrated circuit system with hierarchical capacitor and method of manufacture thereof Grant 8,021,954 - Chu , et al. September 20, 2	2011-09-20
Integrated circuit system employing an elevated drain Grant 7,951,680 - Zhang , et al. May 31, 2	2011-05-31
Integrated Circuit System With High Voltage Transistor And Method Of Manufacture Thereof App 20100320529 - Dong; Yemin ; et al.	2010-12-23
Integrated Circuit System With Hierarchical Capacitor And Method Of Manufacture Thereof App 20100295153 - Chu; Shao-fu Sanford ; et al.	2010-11-25
Method of manufacturing 3-D spiral stacked inductor on semiconductor material Grant 7,721,414 - Sia , et al. May 25, 2	2010-05-25
Integrated Circuit System Employing An Elevated Drain App 20100109097 - Zhang; Guowei ; et al.	2010-05-06
Integrated Circuit System Employing Back End Of Line Via Techniques App 20090294904 - Zhang; Shaoqing ; et al.	2009-12-03
Integrated Circuit System With Double Doped Drain Transistor App 20070210376 - Li; Yisuo ; et al.	2007-09-13
Double polysilicon bipolar transistor Grant 7,268,412 - Verma , et al. September 11, 2	2007-09-11
Self-aligned lateral heterojunction bipolar transistor Grant 7,238,971 - Li , et al. July 3, 2	2007-07-03
Via/line inductor on semiconductor material Grant 7,078,998 - Zhang , et al. July 18, 2	2006-07-18
Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy Grant 7,049,201 - Verma , et al. May 23, 2	2006-05-23
Heterojunction bipolar transistor using reverse emitter window Grant 7,022,578 - Verma , et al. April 4, 2	2006-04-04
Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth Grant 6,972,237 - Verma , et al. December 6, 2	2005-12-06
Self-aligned lateral heterojunction bipolar transistor App 20050196931 - Li, Jian Xun ; et al.	2005-09-08
Double polysilicon bipolar transistor and method of manufacture therefor Grant 6,936,519 - Verma , et al. August 30, 2	2005-08-30
Double polysilicon bipolar transistor App 20050170580 - Verma, Purakh Raj ; et al.	2005-08-04
Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact Grant 6,924,202 - Li , et al. August 2, 2	2005-08-02
Heterojunction BiCMOS integrated circuits and method therefor App 20050145953 - Chan, Lap ; et al.	2005-07-07
Self-aligned lateral heterojunction bipolar transistor Grant 6,908,824 - Li , et al. June 21, 2	2005-06-21
Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth App 20050116254 - Verma, Purakh Raj ; et al.	2005-06-02
Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy App 20050101038 - Verma, Purakh Raj ; et al.	2005-05-12
Self-aligned Lateral Heterojunction Bipolar Transistor App 20050101096 - Li, Jian Xun ; et al.	2005-05-12
Heterojunction Bicmos Semiconductor App 20050098834 - Zheng, Jia Zhen ; et al.	2005-05-12
Heterojunction BiCMOS semiconductor Grant 6,881,976 - Zheng , et al. April 19, 2	2005-04-19
Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact App 20050079658 - Li, Jian Xun ; et al.	2005-04-14
Heterojunction bipolar transistor using reverse emitter window App 20050079678 - Verma, Purakh Raj ; et al.	2005-04-14
Method of manufacturing 3-D spiral stacked inductor on semiconductor material App 20050057335 - Sia, Choon-Beng ; et al.	2005-03-17
3-D spiral stacked inductor on semiconductor material Grant 6,841,847 - Sia , et al. January 11, 2	2005-01-11
Via/line inductor on semiconductor material App 20040140526 - Jiong, Zhang ; et al.	2004-07-22
Via/line inductor on semiconductor material Grant 6,750,750 - Jiong , et al. June 15, 2	2004-06-15
Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology Grant 6,709,918 - Ng , et al. March 23, 2	2004-03-23
3-D spiral stacked inductor on semiconductor material App 20040041234 - Sia, Choon-Beng ; et al.	2004-03-04
Double polysilicon bipolar transistor and method of manufacture therefor App 20040033671 - Verma, Purakh Raj ; et al.	2004-02-19
Via/line inductor on semiconductor material App 20030122649 - Jiong, Zhang ; et al.	2003-07-03
Method For Forming Self-aligned Channel Implants Using A Gate Poly Reverse Mask App 20020127808 - Shao, Kai ; et al.	2002-09-12
Method for forming self-aligned channel implants using a gate poly reverse mask Grant 6,410,394 - Shao , et al. June 25, 2	2002-06-25
Process to control the lateral doping profile of an implanted channel region Grant 6,297,132 - Zhang , et al. October 2, 2	2001-10-02
Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions Grant 6,133,079 - Zhu , et al. October 17, 2	2000-10-17
Modular MOSFETS for high aspect ratio applications Grant 5,874,764 - Hsieh , et al. February 23, 1	1999-02-23

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