Chu; Sanford

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chu; Sanford.The latest application filed is for "integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same".

Company Profile

0.54.47

Chu; Sanford - Poughkeepsie NY
Chu; Sanford - Singapore SG
Chu; Sanford - Leonie Condotel N/A SG
CHU; Sanford - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same Grant 10,115,719 - Singh , et al. October 30, 2	2018-10-30
Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime Grant 9,583,557 - Cheng , et al. February 28, 2	2017-02-28
Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof Grant 9,530,833 - Triyoso , et al. December 27, 2	2016-12-27
Integrated Circuits With Resistor Structures Formed From Mim Capacitor Material And Methods For Fabricating Same App 20160126239 - Singh; Jagar ; et al.	2016-05-05
Integrated Circuits Including A Mimcap Device And Methods Of Forming The Same For Long And Controllable Reliability Lifetime App 20160064472 - Cheng; Lili ; et al.	2016-03-03
Semiconductor Structure Including Capacitors Having Different Capacitor Dielectrics And Method For The Formation Thereof App 20150364535 - Triyoso; Dina H. ; et al.	2015-12-17
P-channel flash with enhanced band-to-band tunneling hot electron injection Grant 9,029,227 - Toh , et al. May 12, 2	2015-05-12
High voltage FINFET structure Grant 9,006,055 - Xiao , et al. April 14, 2	2015-04-14
Diffusion Barrier And Method Of Formation Thereof App 20150008528 - TAN; Shyue Seng ; et al.	2015-01-08
Channel surface technique for fabrication of FinFET devices Grant 8,896,072 - Tan , et al. November 25, 2	2014-11-25
High Voltage Finfet Structure App 20140210009 - Xiao; Han ; et al.	2014-07-31
EEPROM cell Grant 8,664,708 - Jung , et al. March 4, 2	2014-03-04
Dielectric stack Grant 8,664,711 - Jung , et al. March 4, 2	2014-03-04
EEPROM cell Grant 8,659,067 - Jung , et al. February 25, 2	2014-02-25
Asymmetrical transistor device and method of fabrication Grant 8,629,503 - Tan , et al. January 14, 2	2014-01-14
Dielectric Stack App 20140001538 - JUNG; Sung Mun ; et al.	2014-01-02
Dielectric stack Grant 8,541,273 - Jung , et al. September 24, 2	2013-09-24
CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES App 20130187242 - Tan; Chung Foong ; et al.	2013-07-25
Eeprom Cell App 20130161721 - JUNG; Sung Mun ; et al.	2013-06-27
Eeprom Cell App 20130161720 - JUNG; Sung Mun ; et al.	2013-06-27
Diffusion Barrier And Method Of Formation Thereof App 20130087889 - TAN; Shyue Seng ; et al.	2013-04-11
Semiconductor structure including high voltage device Grant 8,410,553 - Koo , et al. April 2, 2	2013-04-02
EEPROM cell Grant 8,383,476 - Jung , et al. February 26, 2	2013-02-26
EEPROM cell Grant 8,383,475 - Jung , et al. February 26, 2	2013-02-26
Channel surface technique for fabrication of FinFET devices Grant 8,349,692 - Tan , et al. January 8, 2	2013-01-08
LDMOS using a combination of enhanced dielectric stress layer and dummy gates Grant 8,334,567 - Chu , et al. December 18, 2	2012-12-18
Diffusion barrier and method of formation thereof Grant 8,324,031 - Tan , et al. December 4, 2	2012-12-04
High performance LDMOS device having enhanced dielectric strain layer Grant 8,293,614 - Chu , et al. October 23, 2	2012-10-23
CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES App 20120228676 - Tan; Chung Foong ; et al.	2012-09-13
P-channel Flash With Enhanced Band-to-band Tunneling Hot Electron Injection App 20120223318 - Toh; Eng Huat ; et al.	2012-09-06
Asymmetrical Transistor Device And Method Of Fabrication App 20120139046 - TAN; Chung Foong ; et al.	2012-06-07
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer App 20120119293 - Chu; Sanford ; et al.	2012-05-17
High performance LDMOS device having enhanced dielectric strain layer Grant 8,163,621 - Chu , et al. April 24, 2	2012-04-24
Dielectric Stack App 20120074537 - JUNG; Sung Mun ; et al.	2012-03-29
Eeprom Cell App 20120074482 - JUNG; Sung Mun ; et al.	2012-03-29
Eeprom Cell App 20120074483 - JUNG; Sung Mun ; et al.	2012-03-29
Asymmetrical transistor device and method of fabrication Grant 8,110,470 - Tan , et al. February 7, 2	2012-02-07
Semiconductor Structure Including High Voltage Device App 20110079850 - KOO; Jeoung Mo ; et al.	2011-04-07
Asymmetrical Transistor Device And Method Of Fabrication App 20110049625 - TAN; Chung Foong ; et al.	2011-03-03
LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates App 20110042743 - CHU; Sanford ; et al.	2011-02-24
Semiconductor structure including high voltage device Grant 7,867,862 - Koo , et al. January 11, 2	2011-01-11
Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process Grant 7,846,805 - Zhang , et al. December 7, 2	2010-12-07
LDMOS using a combination of enhanced dielectric stress layer and dummy gates Grant 7,824,968 - Chu , et al. November 2, 2	2010-11-02
Modular & Scalable Intra-metal Capacitors App 20100038752 - NG; Chit Hwei ; et al.	2010-02-18
Diffusion Barrier And Method Of Formation Thereof App 20090315152 - TAN; Shyue Seng ; et al.	2009-12-24
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer App 20090302385 - Chu; Sanford ; et al.	2009-12-10
SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS App 20090146258 - ZHANG; Shaoqiang ; et al.	2009-06-11
Semiconductor Structure Including High Voltage Device App 20090072310 - KOO; Jeoung Mo ; et al.	2009-03-19
Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process Grant 7,488,662 - Zhang , et al. February 10, 2	2009-02-10
Low Voltage Coefficient Mos Capacitors App 20080191258 - JIA; Tan Li ; et al.	2008-08-14
Method of integrating triple gate oxide thickness Grant 7,410,874 - Verma , et al. August 12, 2	2008-08-12
MOSFET device with low gate contact resistance Grant 7,382,027 - Verma , et al. June 3, 2	2008-06-03
Method of integrating triple gate oxide thickness App 20080124872 - Verma; Purakh Raj ; et al.	2008-05-29
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits Grant 7,323,736 - Yelehanka , et al. January 29, 2	2008-01-29
LDMOS using a combination of enhanced dielectric stress layer and dummy gates App 20080014690 - Chu; Sanford ; et al.	2008-01-17
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks Grant 7,250,669 - Chan , et al. July 31, 2	2007-07-31
Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process App 20070134854 - Zhang; Shaoqiang ; et al.	2007-06-14
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits App 20060207965 - Ramaghandramurthy Pradeep; Yelehanka ; et al.	2006-09-21
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits Grant 7,060,193 - Yelehanka , et al. June 13, 2	2006-06-13
Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies Grant 6,933,188 - Verma , et al. August 23, 2	2005-08-23
Method of making direct contact on gate by using dielectric stop layer App 20050136573 - Rajverma, Purakh ; et al.	2005-06-23
Method of forming an inductor with continuous metal deposition App 20050124131 - Hweing, Chit ; et al.	2005-06-09
Method to fill a trench and tunnel by using ALD seed layer and electroless plating Grant 6,903,013 - Chan , et al. June 7, 2	2005-06-07
Method of fabricating circular or angular spiral MIM capacitors App 20050086780 - Shao, Kai ; et al.	2005-04-28
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks Grant 6,869,884 - Chan , et al. March 22, 2	2005-03-22
Method Of Making Direct Contact On Gate By Using Dielectric Stop Layer App 20050059216 - Verma, Purakh Raj ; et al.	2005-03-17
Method of making direct contact on gate by using dielectric stop layer Grant 6,861,317 - Verma , et al. March 1, 2	2005-03-01
Method of forming an inductor with continuous metal deposition Grant 6,852,605 - Ng , et al. February 8, 2	2005-02-08
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks App 20050009357 - Chan, Lap ; et al.	2005-01-13
Method to enhance inductor Q factor by forming air gaps below inductors Grant 6,835,631 - Zhen , et al. December 28, 2	2004-12-28
Method for forming a MIM capacitor Grant 6,825,080 - Yang , et al. November 30, 2	2004-11-30
Method of blocking nitrogen from thick gate oxide during dual gate CMP Grant 6,821,904 - Pradeep , et al. November 23, 2	2004-11-23
Method to fill a trench and tunnel by using ALD seed layer and electroless plating App 20040229457 - Chan, Lap ; et al.	2004-11-18
Method of forming an inductor with continuous metal deposition App 20040217440 - Ng, Chit Hwei ; et al.	2004-11-04
Method for forming a MIM (metal-insulator-metal) capacitor Grant 6,780,727 - Hwei , et al. August 24, 2	2004-08-24
Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield Grant 6,777,774 - Beng , et al. August 17, 2	2004-08-17
Metal sandwich structure for MIM capacitor onto dual damascene Grant 6,746,914 - Kai , et al. June 8, 2	2004-06-08
Mim And Metal Resistor Formation At Cu Beol Using Only One Extra Mask App 20040087098 - Ng, Chit Hwei ; et al.	2004-05-06
MIM and metal resistor formation at CU beol using only one extra mask Grant 6,730,573 - Ng , et al. May 4, 2	2004-05-04
Method of forming a surface coating layer within an opening within a body by atomic layer deposition Grant 6,716,693 - Chan , et al. April 6, 2	2004-04-06
Silicon-based inductor with varying metal-to-metal conductor spacing Grant 6,714,112 - Beng , et al. March 30, 2	2004-03-30
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks App 20040038542 - Chan, Lap ; et al.	2004-02-26
Method of blocking nitrogen from thick gate oxide during dual gate CMP App 20040023506 - Pradeep, Yelehanka Ramachandramurthy ; et al.	2004-02-05
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits App 20040004054 - Pradeep, Yelehanka Ramachandramurthy ; et al.	2004-01-08
Silicon-based inductor with varying metal-to-metal conductor spacing App 20030210121 - Beng, Sia Choon ; et al.	2003-11-13
Metal sandwich structure for MIM capacitor onto dual damascene App 20030211731 - Kai, Shao ; et al.	2003-11-13
Method for forming a MIM (metal-insulator-metal) capacitor App 20030203584 - Hwei, Ng Chit ; et al.	2003-10-30
Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill Grant 6,638,844 - Verma , et al. October 28, 2	2003-10-28
Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield App 20030197243 - Beng, Sia Choon ; et al.	2003-10-23
Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components Grant 6,608,362 - Kai , et al. August 19, 2	2003-08-19
Darc layer for MIM process integration Grant 6,576,526 - Kai , et al. June 10, 2	2003-06-10
Darc layer for MIM process integration App 20030008467 - Kai, Shao ; et al.	2003-01-09

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