Chu; Chih Hsun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chu; Chih Hsun.The latest application filed is for "oscillator wafer-level-package structure".

Company Profile

0.23.16

Chu; Chih Hsun - Ping Cheng TW
CHU; CHIH-HSUN - PING CHENG CITY TW
Chu; Chih-hsun - Hsinchu TW
Chu; Chih-hsun - Hsinchu City TW
Chu; Chih-Hsun - Hsin-Chu TW
Chu, Chih-Hsun - Hsin-Chu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Crystal oscillator and method for fabricating the same Grant 11,398,797 - Wang , et al. July 26, 2	2022-07-26
Oscillator Wafer-level-package Structure App 20210376792 - CHU; CHIH-HSUN ; et al.	2021-12-02
Specimen preparation for transmission electron microscopy Grant 9,384,942 - Hsieh , et al. July 5, 2	2016-07-05
Specimen Preparation For Transmission Electron Microscopy App 20150194288 - Hsieh; Yong-fen ; et al.	2015-07-09
Specimen preparation for transmission electron microscopy Grant 8,969,827 - Hsieh , et al. March 3, 2	2015-03-03
Specimen Preparation For Tem App 20140007709 - HSIEH; Yong-Fen ; et al.	2014-01-09
Method of fabricating a recess channel transistor Grant 7,531,438 - Chou , et al. May 12, 2	2009-05-12
Solar cell and fabricating process thereof App 20090056807 - Chen; Hsi-Chieh ; et al.	2009-03-05
Photovoltaic Power Device And Manufacturing Method Thereof App 20080302412 - CHEN; Hsi-Chieh ; et al.	2008-12-11
Semicondutor device and manufacturing method thereof Grant 7,462,545 - Chou , et al. December 9, 2	2008-12-09
Reduced Area Dynamic Random Access Memory (dram) Cell And Method For Fabricating The Same App 20080268646 - Butler; Douglas Blaine ; et al.	2008-10-30
Method of fabricating a recess channel transistor App 20070249123 - Chou; Jih-Wen ; et al.	2007-10-25
Method for preparing a gate oxide layer App 20070155187 - Chen; Chung Yi ; et al.	2007-07-05
Method For Manufacturing Non-volatile Memory App 20070128796 - Chu; Chih-Hsun	2007-06-07
Reduced area dynamic random access memory (DRAM) cell and method for fabricating the same App 20070085152 - Butler; Douglas Blaine ; et al.	2007-04-19
Semicondutor Device And Manufacturing Method Thereof App 20070012994 - Chou; Jih-Wen ; et al.	2007-01-18
Method for operating a NAND-array memory module composed of P-type memory cells Grant 6,952,369 - Hsu , et al. October 4, 2	2005-10-04
Integrated circuit embedded with single-poly non-volatile memory Grant 6,920,067 - Hsu , et al. July 19, 2	2005-07-19
Method For Operating A Nand-array Memory Module Composed Of P-type Memory Cells App 20050030789 - Hsu, Ching-Hsiang ; et al.	2005-02-10
Method for programming, erasing and reading a flash memory cell Grant 6,801,456 - Hsu , et al. October 5, 2	2004-10-05
Method of forming an embedded memory including forming three silicon or polysilicon layers Grant 6,787,419 - Chen , et al. September 7, 2	2004-09-07
Method Of Forming An Embedded Memory Including Forming Three Silicon Or Polysilicon Layers App 20040137686 - Chen, Chung-Yi ; et al.	2004-07-15
Integrated Circuit Embedded With Single-poly Non-volatile Memory App 20040125652 - Hsu, Ching-Hsiang ; et al.	2004-07-01
Method for forming EPROM with low leakage Grant 6,740,556 - Hsu , et al. May 25, 2	2004-05-25
Electrically erasable programmable logic device Grant 6,617,637 - Hsu , et al. September 9, 2	2003-09-09
Method for fabricating an embedded dynamic random access memory Grant 6,337,240 - Chu January 8, 2	2002-01-08
Method for restoring an alignment mark after planarization of a dielectric layer Grant 6,290,631 - Chu , et al. September 18, 2	2001-09-18
Method forming shallow trench isolation Grant 6,258,692 - Chu , et al. July 10, 2	2001-07-10
Method For Restoring An Alignment Mark After Planarization Of A Dielectric Layer App 20010001735 - CHU, CHIH-HSUN ; et al.	2001-05-24
Method of reconstructing alignment mark during STI process Grant 6,232,200 - Chu May 15, 2	2001-05-15
Method for forming shallow trench isolation region Grant 6,180,493 - Chu January 30, 2	2001-01-30
Method for fabricating MOSFET having increased effective gate length Grant 6,127,699 - Ni , et al. October 3, 2	2000-10-03
Method of fabricating semiconductor devices with raised doped region structures Grant 6,114,209 - Chu , et al. September 5, 2	2000-09-05
Process for manufacturing semiconductor devices having raised doped regions Grant 6,001,697 - Chang , et al. December 14, 1	1999-12-14
Method of manufacturing a shallow trench isolation for a semiconductor device Grant 5,851,900 - Chu , et al. December 22, 1	1998-12-22
Process for manufacturing a CMOSFET intergrated circuit Grant 5,696,016 - Chen , et al. December 9, 1	1997-12-09
Process for suppressing boron penetration in BF.sub.2 .sup.+ -implanted P.sup.+ -poly-Si gate using inductively-coupled nitrogen plasma Grant 5,629,221 - Chao , et al. May 13, 1	1997-05-13

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