Chow; Yew Tuck

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chow; Yew Tuck.The latest application filed is for "horizontal epitaxy furnace for channel sige formation".

Company Profile

0.8.10

Chow; Yew Tuck - Dresden N/A DE
Chow; Yew Tuck - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Epitaxial channel formation methods and structures Grant 9,548,378 - Kronholz , et al. January 17, 2	2017-01-17
Horizontal epitaxy furnace for channel SiGe formation Grant 9,018,065 - Wasyluk , et al. April 28, 2	2015-04-28
Methods for pFET fabrication using APM solutions Grant 8,658,543 - Wasyluk , et al. February 25, 2	2014-02-25
Tmah Recess For Silicon Germanium In Positive Channel Region For Cmos Device App 20130299874 - Wasyluk; Joanna ; et al.	2013-11-14
Horizontal Epitaxy Furnace For Channel Sige Formation App 20130302973 - Wasyluk; Joanna ; et al.	2013-11-14
Epitaxial Channel Formation Methods And Structures App 20130210216 - Kronholz; Stephan ; et al.	2013-08-15
Methods For Pfet Fabrication Using Apm Solutions App 20130203244 - Wasyluk; Joanna ; et al.	2013-08-08
Nested and isolated transistors with reduced impedance difference Grant 8,143,651 - Widodo , et al. March 27, 2	2012-03-27
Nested And Isolated Transistors With Reduced Impedance Difference App 20100301424 - WIDODO; Johnny ; et al.	2010-12-02
Nested and isolated transistors with reduced impedance difference Grant 7,767,577 - Widodo , et al. August 3, 2	2010-08-03
Nested And Isolated Transistors With Reduced Impedance Difference App 20090206408 - WIDODO; Johnny ; et al.	2009-08-20

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