| Patent | Date |
|---|
Physically unclonable camouflage structure and methods for fabricating same
Grant 11,264,990 - Cocchi , et al. March 1, 2 | 2022-03-01 |
Secure logic locking and configuration with camouflaged programmable micro netlists
Grant 11,163,930 - Chow , et al. November 2, 2 | 2021-11-02 |
Always-on Finfet With Camouflaged Punch Stop Implants For Protecting Integrated Circuits From Reverse Engineering
App 20210249364 - Chow; Lap Wai ; et al. | 2021-08-12 |
Electrically Isolated Gate Contact In Finfet Technology For Camouflaging Integrated Circuits From Reverse Engineering
App 20210249363 - Chow; Lap Wai ; et al. | 2021-08-12 |
Camouflaged FinFET and method for producing same
Grant 10,923,596 - Chow , et al. February 16, 2 | 2021-02-16 |
Secure Logic Locking And Configuration With Camouflaged Programmable Micro Netlists
App 20210004515 - Chow; Lap Wai ; et al. | 2021-01-07 |
Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells
Grant 10,817,638 - Wang , et al. October 27, 2 | 2020-10-27 |
Method And Apparatus For Camouflaging An Integrated Circuit Using Virtual Camouflage Cells
App 20200311222 - Wang; Bryan J. ; et al. | 2020-10-01 |
Physically Unclonable Camouflage Structure And Methods For Fabricating Same
App 20200295763 - Cocchi; Ronald P. ; et al. | 2020-09-17 |
Camouflaged Finfet And Method For Producing Same
App 20200287040 - Chow; Lap Wai ; et al. | 2020-09-10 |
Obfuscated Shift Registers For Integrated Circuits
App 20200285719 - Wang; Bryan J. ; et al. | 2020-09-10 |
Secure logic locking and configuration with camouflaged programmable micro netlists
Grant 10,691,860 - Chow , et al. | 2020-06-23 |
Physically unclonable camouflage structure and methods for fabricating same
Grant 10,574,237 - Cocchi , et al. Feb | 2020-02-25 |
Method And Apparatus For Obfuscating An Integrated Circuit With Camouflaged Gates And Logic Encryption
App 20190258766 - Wang; Bryan J. ; et al. | 2019-08-22 |
Secure Logic Locking And Configuration With Camouflaged Programmable Micro Netlists
App 20180341737 - Chow; Lap Wai ; et al. | 2018-11-29 |
Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
Grant 9,940,425 - Wang , et al. April 10, 2 | 2018-04-10 |
Physically Unclonable Camouflage Structure And Methods For Fabricating Same
App 20170359071 - Cocchi; Ronald P. ; et al. | 2017-12-14 |
Physically unclonable camouflage structure and methods for fabricating same
Grant 9,735,781 - Cocchi , et al. August 15, 2 | 2017-08-15 |
Method And Apparatus For Camouflaging A Standard Cell Based Integrated Circuit With Micro Circuits And Post Processing
App 20170091368 - Wang; Bryan Jason ; et al. | 2017-03-30 |
Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
Grant 9,542,520 - Wang , et al. January 10, 2 | 2017-01-10 |
Physically Unclonable Camouflage Structure And Methods For Fabricating Same
App 20160197616 - Cocchi; Ronald P. ; et al. | 2016-07-07 |
Method and apparatus for camouflaging a standard cell based integrated circuit
Grant 9,355,199 - Chow , et al. May 31, 2 | 2016-05-31 |
Use of silicide block process to camouflage a false transistor
Grant 8,679,908 - Chow , et al. March 25, 2 | 2014-03-25 |
Battery chargers, electrical systems, and rechargeable battery charging methods
Grant 8,598,845 - Lim , et al. December 3, 2 | 2013-12-03 |
Method And Apparatus For Camouflaging A Standard Cell Based Integrated Circuit With Micro Circuits And Post Processing
App 20130300454 - Wang DiMarzio; Bryan Jason ; et al. | 2013-11-14 |
Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
Grant 8,564,073 - Clark, Jr. , et al. October 22, 2 | 2013-10-22 |
Integrated circuit modification using well implants
Grant 8,524,553 - Chow , et al. September 3, 2 | 2013-09-03 |
Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
Grant 8,510,700 - Cocchi , et al. August 13, 2 | 2013-08-13 |
Method And Apparatus For Camouflaging A Standard Cell Based Integrated Circuit
App 20130191803 - Chow; Lap Wai ; et al. | 2013-07-25 |
Method and apparatus for camouflaging a standard cell based integrated circuit
Grant 8,418,091 - Chow , et al. April 9, 2 | 2013-04-09 |
Cryptographic bus architecture for the prevention of differential power analysis
Grant 8,296,577 - Shu , et al. October 23, 2 | 2012-10-23 |
Conductive channel pseudo block process and circuit to inhibit reverse engineering
Grant 8,258,583 - Chow , et al. September 4, 2 | 2012-09-04 |
Method And Apparatus For Camouflaging A Standard Cell Based Integrated Circuit With Micro Circuits And Post Processing
App 20120139582 - Cocchi; Ronald P. ; et al. | 2012-06-07 |
Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis
App 20120144205 - Shu; David B. ; et al. | 2012-06-07 |
Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
Grant 8,168,487 - Clark, Jr. , et al. May 1, 2 | 2012-05-01 |
Camouflaging a standard cell based integrated circuit
Grant 8,151,235 - Chow , et al. April 3, 2 | 2012-04-03 |
Building block for a secure CMOS logic cell library
Grant 8,111,089 - Cocchi , et al. February 7, 2 | 2012-02-07 |
Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis
Grant 8,095,993 - Shu , et al. January 10, 2 | 2012-01-10 |
Cryptographic architecture with random instruction masking to thwart differential power analysis
Grant 8,065,532 - Shu , et al. November 22, 2 | 2011-11-22 |
Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
Grant 8,049,281 - Chow , et al. November 1, 2 | 2011-11-01 |
Cryptographic CPU architecture with random instruction masking to thwart differential power analysis
Grant 7,949,883 - Shu , et al. May 24, 2 | 2011-05-24 |
Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
Grant 7,935,603 - Chow , et al. May 3, 2 | 2011-05-03 |
Conductive channel pseudo block process and circuit to inhibit reverse engineering
Grant 7,888,213 - Chow , et al. February 15, 2 | 2011-02-15 |
Building Block For A Secure Cmos Logic Cell Library
App 20100301903 - Cocchi; Ronald P. ; et al. | 2010-12-02 |
Battery Chargers, Electrical Systems, and Rechargeable Battery Charging Methods
App 20100264879 - Lim; Khoon Cheng ; et al. | 2010-10-21 |
Method and apparatus for camouflaging a printed circuit board
App 20100213974 - Chow; Lap Wai ; et al. | 2010-08-26 |
Method And Apparatus For Camouflaging A Standard Cell Based Integrated Circuit
App 20100218158 - Chow; Lap Wai ; et al. | 2010-08-26 |
Integrated Circuit Modification Using Well Implants
App 20090170255 - Chow; Lap-Wai ; et al. | 2009-07-02 |
Covert transformation of transistor properties as a circuit protection method
Grant 7,541,266 - Chow , et al. June 2, 2 | 2009-06-02 |
Integrated circuit modification using well implants
Grant 7,514,755 - Chow , et al. April 7, 2 | 2009-04-07 |
Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
App 20080079082 - Clark; William M. ; et al. | 2008-04-03 |
Use of silicon block process step to camouflage a false transistor
Grant 7,344,932 - Chow , et al. March 18, 2 | 2008-03-18 |
Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
Grant 7,294,935 - Chow , et al. November 13, 2 | 2007-11-13 |
Use of silicon block process step to camouflage a false transistor
App 20070243675 - Chow; Lap-Wai ; et al. | 2007-10-18 |
Covert transformation of transistor properties as a circuit protection method
App 20070224750 - Chow; Lap-Wai ; et al. | 2007-09-27 |
Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis
App 20070180541 - Shu; David B. ; et al. | 2007-08-02 |
Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
Grant 7,242,063 - Chow , et al. July 10, 2 | 2007-07-10 |
Covert transformation of transistor properties as a circuit protection method
Grant 7,217,977 - Chow , et al. May 15, 2 | 2007-05-15 |
Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
Grant 7,166,515 - Clark, Jr. , et al. January 23, 2 | 2007-01-23 |
Conductive channel pseudo block process and circuit to inhibit reverse engineering
App 20060157803 - Chow; Lap-Wai ; et al. | 2006-07-20 |
Conductive channel pseudo block process and circuit to inhibit reverse engineering
Grant 7,049,667 - Chow , et al. May 23, 2 | 2006-05-23 |
Integrated circuit with reverse engineering protection
Grant 7,008,873 - Chow , et al. March 7, 2 | 2006-03-07 |
Use of silicon block process step to camouflage a false transistor
Grant 6,979,606 - Chow , et al. December 27, 2 | 2005-12-27 |
Cryptographic architecture with random instruction masking to thwart differential power analysis
App 20050271202 - Shu, David B. ; et al. | 2005-12-08 |
Cryptographic bus architecture for the prevention of differential power analysis
App 20050273630 - Shu, David B. ; et al. | 2005-12-08 |
Cryptographic CPU architecture with random instruction masking to thwart differential power analysis
App 20050273631 - Shu, David B. ; et al. | 2005-12-08 |
Covert transformation of transistor properties as a circuit protection method
App 20050230787 - Chow, Lap-Wai ; et al. | 2005-10-20 |
Memory with a bit line block and/or a word line block for preventing reverse engineering
Grant 6,940,764 - Clark, Jr. , et al. September 6, 2 | 2005-09-06 |
Multilayered integrated circuit with extraneous conductive traces
Grant 6,924,552 - Baukus , et al. August 2, 2 | 2005-08-02 |
Integrated circuit with reverse engineering protection
App 20050161748 - Chow, Lap-Wai ; et al. | 2005-07-28 |
Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
Grant 6,919,600 - Baukus , et al. July 19, 2 | 2005-07-19 |
Integrated circuit with reverse engineering protection
Grant 6,897,535 - Chow , et al. May 24, 2 | 2005-05-24 |
Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same
Grant 6,893,916 - Baukus , et al. May 17, 2 | 2005-05-17 |
Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
Grant 6,815,816 - Clark, Jr. , et al. November 9, 2 | 2004-11-09 |
Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
Grant 6,791,191 - Chow , et al. September 14, 2 | 2004-09-14 |
Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
App 20040164361 - Baukus, James P. ; et al. | 2004-08-26 |
Integrated circuit structure with programmable connector/isolator
Grant 6,774,413 - Baukus , et al. August 10, 2 | 2004-08-10 |
Integrated circuit modification using well implants
App 20040144998 - Chow, Lap-Wai ; et al. | 2004-07-29 |
Multilayered integrated circuit with extraneous conductive traces
App 20040119165 - Baukus, James P. ; et al. | 2004-06-24 |
Use of silicon block process step to camouflage a false transistor
App 20040099912 - Chow, Lap-Wai ; et al. | 2004-05-27 |
Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
Grant 6,740,942 - Baukus , et al. May 25, 2 | 2004-05-25 |
Conductive channel pseudo block process and circuit to inhibit reverse engineering
App 20040061186 - Chow, Lap-Wai ; et al. | 2004-04-01 |
Memory with a bit line block and/or a word line block for preventing reverse engineering
App 20040047188 - Clark ,Jr, William M. ; et al. | 2004-03-11 |
Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same
App 20040012067 - Baukus, James P. ; et al. | 2004-01-22 |
CMOS-compatible MEM switches and method of making
Grant 6,667,245 - Chow , et al. December 23, 2 | 2003-12-23 |
Integrated circuit with reverse engineering protection
App 20030214002 - Chow, Lap-Wai ; et al. | 2003-11-20 |
Process for fabricating secure integrated circuit
Grant 6,613,661 - Baukus , et al. September 2, 2 | 2003-09-02 |
Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
App 20020190355 - Baukus, James P. ; et al. | 2002-12-19 |
Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same
App 20020192878 - Baukus, James P. ; et al. | 2002-12-19 |
Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
App 20020173131 - Clark, William M. JR. ; et al. | 2002-11-21 |
Memory with a bit line block and/or a word line block for preventing reverse engineering
Grant 6,459,629 - Clark, Jr. , et al. October 1, 2 | 2002-10-01 |
Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
App 20020096777 - Chow, Lap-Wai ; et al. | 2002-07-25 |
Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
App 20020096776 - Chow, Lap-Wai ; et al. | 2002-07-25 |
Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in integrated circuits
App 20020096744 - Chow, Lap-Wai ; et al. | 2002-07-25 |
CMOS-compatible MEM switches and method of making
Grant 6,396,368 - Chow , et al. May 28, 2 | 2002-05-28 |
CMOS-compatible MEM switches and method of making
App 20020055260 - Chow, Lap-Wai ; et al. | 2002-05-09 |
Secure integrated circuit
Grant 6,294,816 - Baukus , et al. September 25, 2 | 2001-09-25 |
Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering
Grant 6,117,762 - Baukus , et al. September 12, 2 | 2000-09-12 |
Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
Grant 6,064,110 - Baukus , et al. May 16, 2 | 2000-05-16 |
Split sense amplifier and staging buffer for wide memory architecture
Grant 5,991,209 - Chow November 23, 1 | 1999-11-23 |
Camouflaged circuit structure with step implants
Grant 5,973,375 - Baukus , et al. October 26, 1 | 1999-10-26 |
Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle
Grant 5,928,350 - Shu , et al. July 27, 1 | 1999-07-27 |
Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
Grant 5,930,663 - Baukus , et al. July 27, 1 | 1999-07-27 |
Integrated circuit security system and method with implanted interconnections
Grant 5,866,933 - Baukus , et al. February 2, 1 | 1999-02-02 |
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