Chou; Yi-Teh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chou; Yi-Teh.The latest application filed is for "bump-on-trace structures with high assembly yield".

Company Profile

0.7.5

Chou; Yi-Teh - Taipei TW
Chou; Yi-Teh - Taipei City TW
Chou; Yi-Teh - Hsin-Chu TW
Chou; Yi-Teh - Hsinchu N/A TW
Chou; Yi-Teh - Hsinchu City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bump-on-trace structures with high assembly yield Grant 10,050,000 - Huang , et al. August 14, 2	2018-08-14
Bump-on-Trace Structures with High Assembly Yield App 20170005059 - Huang; Chih-Fan ; et al.	2017-01-05
Bump-on-trace structures with high assembly yield Grant 9,472,525 - Huang , et al. October 18, 2	2016-10-18
Bump-on-Trace Structures with High Assembly Yield App 20160086901 - Huang; Chih-Fan ; et al.	2016-03-24
Bump-on-trace structures with high assembly yield Grant 9,209,149 - Huang , et al. December 8, 2	2015-12-08
Bump-on-Trace Structures with High Assembly Yield App 20150130051 - Huang; Chih-Fan ; et al.	2015-05-14
Semiconductor structure and fabricating method thereof Grant 8,609,460 - Liu , et al. December 17, 2	2013-12-17
High-gain complementary inverter with ambipolar thin film transistors and fabrication thereof Grant 8,563,974 - Liu , et al. October 22, 2	2013-10-22
High-Gain Complementary Inverter with Ambipolar Thin Film Transistors and Fabrication Thereof App 20120298982 - Liu; Po-Tsun ; et al.	2012-11-29
Semiconductor Structure And Fabricating Method Thereof App 20120061661 - Liu; Po-Tsun ; et al.	2012-03-15

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