loadpatents
name:-0.0096909999847412
name:-0.0083189010620117
name:-0.010460138320923
CHOU; Ya-Chi Patent Filings

CHOU; Ya-Chi

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHOU; Ya-Chi.The latest application filed is for "integrated circuit having fins crossing cell boundary".

Company Profile
10.7.9
  • CHOU; Ya-Chi - Hsinchu City TW
  • Chou; Ya-Chi - Hsinchu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated Circuit Having Fins Crossing Cell Boundary
App 20210313319 - SUE; Pin-Dai ;   et al.
2021-10-07
Buried Metal Track and Methods Forming Same
App 20210242212 - Wang; Pochun ;   et al.
2021-08-05
Buried metal track and methods forming same
Grant 11,004,855 - Wang , et al. May 11, 2
2021-05-11
Integrated Circuit And Method Of Manufacturing Same
App 20200350250 - WANG; Pochun ;   et al.
2020-11-05
Method and system for pin layout
Grant 10,796,060 - Chang , et al. October 6, 2
2020-10-06
Integrated circuit and method of manufacturing same
Grant 10,734,321 - Wang , et al.
2020-08-04
Semiconductor device having engineering change order (ECO) cells and method of using
Grant 10,553,575 - Tien , et al. Fe
2020-02-04
Buried Metal Track and Methods Forming Same
App 20190341387 - Wang; Pochun ;   et al.
2019-11-07
Buried metal track and methods forming same
Grant 10,446,555 - Wang , et al. Oc
2019-10-15
Method And System For Pin Layout
App 20190243940 - CHANG; FONG-YUAN ;   et al.
2019-08-08
Method and system for pin layout
Grant 10,268,796 - Chang , et al.
2019-04-23
Buried Metal Track and Methods Forming Same
App 20190067290 - Wang; Pochun ;   et al.
2019-02-28
Method And System For Pin Layout
App 20180075181 - CHANG; FONG-YUAN ;   et al.
2018-03-15
Semiconductor Device Having Engineering Change Order (eco) Cells And Method Of Using
App 20180076190 - TIEN; Li-Chun ;   et al.
2018-03-15
Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
Grant 9,831,230 - Tien , et al. November 28, 2
2017-11-28
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20150048424 - TIEN; Li-Chun ;   et al.
2015-02-19

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