loadpatents
name:-0.0029721260070801
name:-0.027933835983276
name:-0.00055098533630371
Chou; William T. Patent Filings

Chou; William T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chou; William T..The latest application filed is for "method of fabricating a substrate with a via connection".

Company Profile
0.23.2
  • Chou; William T. - Cupertino CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods of planarizing structures on wafers and substrates by polishing
Grant 6,733,685 - Beilin , et al. May 11, 2
2004-05-11
Method of fabricating a substrate with a via connection
Grant 6,662,443 - Chou , et al. December 16, 2
2003-12-16
Method of fabricating a substrate with a via connection
App 20020000037 - Chou, William T. ;   et al.
2002-01-03
Methods of planarizing structures on wafers and substrates by polishing
App 20010042734 - Beilin, Solomon I. ;   et al.
2001-11-22
Method for electroplating vias or through holes in substrates having conductors on both sides
Grant 6,197,664 - Lee , et al. March 6, 2
2001-03-06
Method of fabrication of multiple-layer high density substrate
Grant 6,187,652 - Chou , et al. February 13, 2
2001-02-13
Controlled impedance interposer substrate and method of making
Grant 6,102,710 - Beilin , et al. August 15, 2
2000-08-15
High density signal interposer with power and ground wrap
Grant 6,081,026 - Wang , et al. June 27, 2
2000-06-27
Pattern or via structure formed through supplemental electron beam exposure and development to remove image residue
Grant 5,942,373 - Chou , et al. August 24, 1
1999-08-24
Methods of planarizing structures on wafers and substrates by polishing
Grant 5,916,453 - Beilin , et al. June 29, 1
1999-06-29
Methods of etching through wafers and substrates with a composite etch stop layer
Grant 5,891,354 - Lee , et al. April 6, 1
1999-04-06
Controlled impedence interposer substrate
Grant 5,854,534 - Beilin , et al. December 29, 1
1998-12-29
Method of forming a pattern or via structure utilizing supplemental electron beam exposure and development to remove image residue
Grant 5,789,140 - Chou , et al. August 4, 1
1998-08-04
Method of making a multichip module substrate
Grant 5,778,529 - Beilin , et al. July 14, 1
1998-07-14
Fabrication procedure for a stable post
Grant 5,722,162 - Chou , et al. March 3, 1
1998-03-03
Electron-beam treatment procedure for patterned mask layers
Grant 5,660,957 - Chou , et al. August 26, 1
1997-08-26
Substrate with thin film capacitor and insulating plug
Grant 5,652,693 - Chou , et al. July 29, 1
1997-07-29
Multichip module substrate
Grant 5,544,017 - Beilin , et al. August 6, 1
1996-08-06
Functional substrates for packaging semiconductor chips
Grant 5,475,262 - Wang , et al. December 12, 1
1995-12-12
Process for fabricating a substrate with thin film capacitor and insulating plug
Grant 5,455,064 - Chou , et al. October 3, 1
1995-10-03
Method for fabricating thin-film interconnector
Grant 5,419,038 - Wang , et al. May 30, 1
1995-05-30
Functional substrates for packaging semiconductor chips
Grant 5,382,827 - Wang , et al. January 17, 1
1995-01-17
Method of curing thin films of organic dielectric material
Grant 5,376,586 - Beilin , et al. December 27, 1
1994-12-27
Wire interconnect structures for connecting an integrated circuit to a substrate
Grant 5,334,804 - Love , et al. August 2, 1
1994-08-02
Process for fabricating a substrate with thin film capacitor
Grant 5,323,520 - Peters , et al. June 28, 1
1994-06-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed