Chou; Hsueh-Chih
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chou; Hsueh-Chih.The latest application filed is for "semiconductor structure".
- Chou; Hsueh-Chih - Tainan TW
- CHOU; HSUEH-CHIH - TAINAN CITY TW
| Patent | Date |
|---|---|
| System and method of timing characterization for semiconductor circuit Grant 11,270,052 - Tu , et al. March 8, 2 | 2022-03-08 |
| Semiconductor Structure App 20210280608 - CHOU; HSUEH-CHIH ; et al. | 2021-09-09 |
| Semiconductor structure Grant 11,037,957 - Chou , et al. June 15, 2 | 2021-06-15 |
| System And Method Of Timing Characterization For Semiconductor Circuit App 20200410152 - TU; CHIA HAO ; et al. | 2020-12-31 |
| System and method of timing characterization for semiconductor circuit Grant 10,824,784 - Tu , et al. November 3, 2 | 2020-11-03 |
| Semiconductor Structure App 20200286919 - CHOU; HSUEH-CHIH ; et al. | 2020-09-10 |
| Semiconductor structure Grant 10,685,982 - Chou , et al. | 2020-06-16 |
| System And Method Of Timing Characterization For Semiconductor Circuit App 20200110912 - TU; CHIA HAO ; et al. | 2020-04-09 |
| Semiconductor Structure App 20190164992 - CHOU; HSUEH-CHIH ; et al. | 2019-05-30 |
| Layered decoding architecture with reduced number of hardware buffers for LDPC codes Grant 9,048,872 - Ueng , et al. June 2, 2 | 2015-06-02 |
| Layered Decoding Architecture With Reduced Number Of Hardware Buffers For Ldpc Codes App 20140281786 - Ueng; Yeong-Luh ; et al. | 2014-09-18 |
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