loadpatents
name:-0.02544903755188
name:-0.20696711540222
name:-0.0057079792022705
Chou; Chien-Chun Patent Filings

Chou; Chien-Chun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chou; Chien-Chun.The latest application filed is for "various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets".

Company Profile
2.33.26
  • Chou; Chien-Chun - Saratoga CA
  • Chou; Chien-Chun - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Reordering responses in a high performance on-chip network
Grant 10,664,421 - Chan , et al.
2020-05-26
Reordering responses in a high performance on-chip network
Grant 10,303,628 - Chan , et al.
2019-05-28
Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
Grant 10,062,422 - Wingard , et al. August 28, 2
2018-08-28
Various Methods And Apparatus For Configurable Mapping Of Address Regions Onto One Or More Aggregate Targets
App 20170140800 - Wingard; Drew E. ;   et al.
2017-05-18
Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering
Grant 9,495,290 - Wingard , et al. November 15, 2
2016-11-15
Reordering Responses in a High Performance On-Chip Network
App 20160188501 - Chan; Jeremy ;   et al.
2016-06-30
Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary
Grant 9,292,436 - Wingard , et al. March 22, 2
2016-03-22
Methods and apparatuses for time annotated transaction level modeling
Grant 9,087,036 - Chou , et al. July 21, 2
2015-07-21
Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
Grant 8,972,995 - Srinivasan , et al. March 3, 2
2015-03-03
Transaction co-validation across abstraction layers
Grant 8,868,397 - Alexanian , et al. October 21, 2
2014-10-21
Method and apparatus for establishing a quality of service model
Grant 8,504,992 - Weber , et al. August 6, 2
2013-08-06
Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
Grant 8,438,320 - Srinivasan , et al. May 7, 2
2013-05-07
Interconnect implementing internal controls
Grant 8,407,433 - Wingard , et al. March 26, 2
2013-03-26
Performance software instrumentation and analysis for electronic design automation
Grant 8,229,723 - Srinivasan , et al. July 24, 2
2012-07-24
Interconnect That Eliminates Routing Congestion And Manages Simultaneous Transactions
App 20120036296 - Wingard; Drew E. ;   et al.
2012-02-09
Apparatus And Methods To Concurrently Perform Per-thread As Well As Per-tag Memory Access Scheduling Within A Thread And Across Two Or More Threads
App 20120036509 - SRINIVASAN; KRISHNAN ;   et al.
2012-02-09
Various methods and apparatus for address tiling
Grant 8,108,648 - Srinivasan , et al. January 31, 2
2012-01-31
Method and system for a database to monitor and analyze performance of an electronic design
Grant 8,073,820 - Srinivasan , et al. December 6, 2
2011-12-06
Method and system to monitor, debug, and analyze performance of an electronic design
Grant 8,032,329 - Chou , et al. October 4, 2
2011-10-04
Various methods and apparatuses for cycle accurate C-models of components
Grant 8,020,124 - Alexanian , et al. September 13, 2
2011-09-13
Method And Apparatus For Establishing A Quality Of Service Model
App 20100211935 - Weber; Wolf-Dietrich ;   et al.
2010-08-19
Method And System To Monitor, Debug, And Analyze Performance Of An Electronic Design
App 20100057400 - Chou; Chien-Chun ;   et al.
2010-03-04
Various Methods And Apparatus For Address Tiling And Channel Interleaving Throughout The Integrated System
App 20100042759 - Srinivasan; Krishnan ;   et al.
2010-02-18
Composing on-chip interconnects with configurable interfaces
Grant 7,660,932 - Chou , et al. February 9, 2
2010-02-09
Method and apparatus for automatic configuration of multiple on-chip interconnects
Grant 7,603,441 - Synek , et al. October 13, 2
2009-10-13
Method And System For A Database To Monitor And Analyze Performance Of An Electronic Design
App 20090254525 - Srinivasan; Krishnan ;   et al.
2009-10-08
Various Methods And Apparatus For Address Tiling
App 20090235020 - Srinivasan; Krishnan ;   et al.
2009-09-17
Performance Software Instrumentation And Analysis For Electronic Design Automation
App 20090150857 - SRINIVASAN; KRISHNAN ;   et al.
2009-06-11
Interconnect Implementing Internal Controls
App 20080320268 - Wingard; Drew E. ;   et al.
2008-12-25
Various Methods And Apparatus To Support Outstanding Requests To Multiple Targets While Maintaining Transaction Ordering
App 20080320476 - Wingard; Drew E. ;   et al.
2008-12-25
Various Methods And Apparatus For Configurable Mapping Of Address Regions Onto One Or More Aggregate Targets
App 20080320255 - Wingard; Drew E. ;   et al.
2008-12-25
Various Methods And Apparatus To Support Transactions Whose Data Address Sequence Within That Transaction Crosses An Interleaved Channel Address Boundary
App 20080320254 - Wingard; Drew E. ;   et al.
2008-12-25
Various Methods And Apparatuses For Cycle Accurate C-models Of Components
App 20080263486 - Alexanian; Herve ;   et al.
2008-10-23
Composing On-chip Interconnects With Configurable Interfaces
App 20080140903 - Chou; Chien-Chun ;   et al.
2008-06-12
Transaction Co-Validation Across Abstraction Layers
App 20080120082 - Alexanian; Herve Jacques ;   et al.
2008-05-22
Transaction co-validation across abstraction layers
App 20080120085 - Alexanian; Herve Jacques ;   et al.
2008-05-22
Composing on-chip interconnects with configurable interfaces
Grant 7,356,633 - Weber , et al. April 8, 2
2008-04-08
Scalable low bandwidth multicast handling in mixed core systems
Grant 7,302,691 - Masri , et al. November 27, 2
2007-11-27
Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems
Grant 7,266,786 - Chou , et al. September 4, 2
2007-09-04
On-chip inter-network performance optimization using configurable performance parameters
Grant 7,254,603 - Weber , et al. August 7, 2
2007-08-07
Method and apparatus for error handling in networks
Grant 7,243,264 - Weber , et al. July 10, 2
2007-07-10
Communication system and method with configurable posting points
Grant 7,194,566 - Wingard , et al. March 20, 2
2007-03-20
Method and apparatus for speculative response arbitration to improve system latency
Grant 6,976,106 - Tomlinson , et al. December 13, 2
2005-12-13
Method and apparatus for automatic configuration of multiple on-chip interconnects
App 20040128341 - Synek, Kamil ;   et al.
2004-07-01
Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems
App 20040088566 - Chou, Chien-Chun ;   et al.
2004-05-06
Method and apparatus for error handling in networks
App 20040088607 - Weber, Wolf-Dietrich ;   et al.
2004-05-06
Method and apparatus for speculative response arbitration to improve system latency
App 20040088458 - Tomlinson, Jay S. ;   et al.
2004-05-06
Scalable low bandwidth multicast handling in mixed core systems
App 20030212743 - Masri, Nabil N. ;   et al.
2003-11-13
Communication system and method with configurable posting points
App 20030208553 - Wingard, Drew E. ;   et al.
2003-11-06
Composing on-chip interconnects with configurable interfaces
App 20030208566 - Weber, Wolf-Dietrich ;   et al.
2003-11-06
On -chip inter-network performance optimization using configurable performance parameters
App 20030208611 - Weber, Wolf-Dietrich ;   et al.
2003-11-06

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