loadpatents
Patent applications and USPTO patent grants for CHOU; Chia-Jen.The latest application filed is for "package method of a modular stacked semiconductor package".
Patent | Date |
---|---|
Package Method Of A Modular Stacked Semiconductor Package App 20220130813 - Chen; Yi-hsin ;   et al. | 2022-04-28 |
Semiconductor device package with a stress relax pattern Grant 10,249,573 - Su , et al. | 2019-04-02 |
Fault detection and classification matching Grant 10,126,210 - Chou , et al. November 13, 2 | 2018-11-13 |
Semiconductor device package with a stress relax pattern App 20180269160 - Su; Ting-Feng ;   et al. | 2018-09-20 |
Fan-out wafer level package structure Grant 9,899,287 - Su , et al. February 20, 2 | 2018-02-20 |
Fan-out Wafer Level Package Structure App 20170372981 - Su; Ting-Feng ;   et al. | 2017-12-28 |
Heat-dissipating Semiconductor Package For Lessening Package Warpage App 20170358543 - Chou; Chia-Jen | 2017-12-14 |
Heat-dissipating semiconductor package for lessening package warpage Grant 9,842,811 - Chou December 12, 2 | 2017-12-12 |
Manufacturing method of package structure Grant 9,831,219 - Chuang , et al. November 28, 2 | 2017-11-28 |
Manufacturing Method Of Package Structure App 20170309597 - Chuang; Yong-Cheng ;   et al. | 2017-10-26 |
Fault Detection And Classification Matching App 20170030807 - CHOU; Chia-Jen ;   et al. | 2017-02-02 |
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