Chou; Anthony I-Chih

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chou; Anthony I-Chih.The latest application filed is for "thick gate oxide fet integrated with fdsoi without additional thick oxide formation".

Company Profile

1.10.9

Chou; Anthony I-Chih - Beacon NY
Chou; Anthony I-Chih - Hopewell Junction NY
Chou; Anthony I-Chih - Fishkill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Thick Gate Oxide Fet Integrated With Fdsoi Without Additional Thick Oxide Formation App 20190386130 - Chou; Anthony I-Chih ; et al.	2019-12-19
Thick Gate Oxide Fet Integrated With Fdsoi Without Additional Thick Oxide Formation App 20170170265 - Chou; Anthony I-Chih ; et al.	2017-06-15
Fin-type metal-semiconductor resistors and fabrication methods thereof Grant 9,595,518 - Chou , et al. March 14, 2	2017-03-14
Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication Grant 9,401,325 - Chou , et al. July 26, 2	2016-07-26
Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors Grant 9,269,786 - Chou , et al. February 23, 2	2016-02-23
Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors App 20150084132 - Chou; Anthony I-Chih ; et al.	2015-03-26
Planar Polysilicon Regions For Precision Resistors And Electrical Fuses And Method Of Fabrication App 20140252539 - Chou; Anthony I-Chih ; et al.	2014-09-11
Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage Grant 8,829,616 - Chou , et al. September 9, 2	2014-09-09
Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication Grant 8,816,473 - Kumar , et al. August 26, 2	2014-08-26
Method And Structure For Body Contacted Fet With Reduced Body Resistance And Source To Drain Contact Leakage App 20140117409 - Chou; Anthony I-Chih ; et al.	2014-05-01
Electrical Mask Inspection App 20130087787 - Kumar; Arvind ; et al.	2013-04-11
Electrical mask inspection Grant 8,343,781 - Kumar , et al. January 1, 2	2013-01-01
Electrical Mask Inspection App 20120068174 - Kumar; Arvind ; et al.	2012-03-22
Method for forming semiconductor devices having reduced gate edge leakage current Grant 7,456,115 - Chou , et al. November 25, 2	2008-11-25
Method For Forming Semiconductor Devices Having Reduced Gate Edge Leakage Current App 20070010050 - Chou; Anthony I-Chih ; et al.	2007-01-11
Forming gate oxides having multiple thicknesses Grant 7,160,771 - Chou , et al. January 9, 2	2007-01-09
Forming gate oxides having multiple thicknesses App 20050118764 - Chou, Anthony I-Chih ; et al.	2005-06-02
Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby Grant 6,821,833 - Chou , et al. November 23, 2	2004-11-23

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