CHONG; YUNG FU

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHONG; YUNG FU.The latest application filed is for "contact via structures of semiconductor devices".

Company Profile

2.42.43

CHONG; YUNG FU - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Contact Via Structures Of Semiconductor Devices App 20220310444 - CHONG; YUNG FU ; et al.	2022-09-29
Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures Grant 10,566,441 - Nong , et al. Feb	2020-02-18
Transistor with source-drain silicide pullback Grant 10,395,987 - Yeo , et al. A	2019-08-27
Methods Of Forming Integrated Circuits With Solutions To Interlayer Dielectric Void Formation Between Gate Structures App 20190252515 - Nong; Hao ; et al.	2019-08-15
Transistor With Source-drain Silicide Pullback App 20170200649 - YEO; Chia Ching ; et al.	2017-07-13
Methods for fabricating device substrates and integrated circuits Grant 9,390,962 - Ko , et al. July 12, 2	2016-07-12
Device Substrates, Integrated Circuits And Methods For Fabricating Device Substrates And Integrated Circuits App 20160172236 - Ko; Lian Hoon ; et al.	2016-06-16
Diffusion Barrier And Method Of Formation Thereof App 20150008528 - TAN; Shyue Seng ; et al.	2015-01-08
Strained channel transistor and method of fabrication thereof Grant 8,912,567 - Chong , et al. December 16, 2	2014-12-16
Substantially L-shaped silicide for contact Grant 8,643,119 - Luo , et al. February 4, 2	2014-02-04
Method to control source/drain stressor profiles for stress engineering Grant 8,450,775 - Chong , et al. May 28, 2	2013-05-28
Diffusion Barrier And Method Of Formation Thereof App 20130087889 - TAN; Shyue Seng ; et al.	2013-04-11
Diffusion barrier and method of formation thereof Grant 8,324,031 - Tan , et al. December 4, 2	2012-12-04
Formation of raised source/drain structures in NFET with embedded SiGe in PFET Grant 8,288,825 - Chong , et al. October 16, 2	2012-10-16
Semiconductor system using germanium condensation Grant 8,211,761 - Tan , et al. July 3, 2	2012-07-03
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same Grant 8,138,055 - Han , et al. March 20, 2	2012-03-20
Method To Control Source/drain Stressor Profiles For Stress Engineering App 20120001228 - CHONG; Yung Fu ; et al.	2012-01-05
Method to control source/drain stressor profiles for stress engineering Grant 8,017,487 - Chong , et al. September 13, 2	2011-09-13
Integrated circuit isolation system Grant 7,972,921 - Chong , et al. July 5, 2	2011-07-05
Embedded stressor structure and process Grant 7,939,413 - Chong , et al. May 10, 2	2011-05-10
Formation of strained Si channel and Si.sub.1-xGe.sub.x source/drain structures using laser annealing Grant 7,892,905 - Ong , et al. February 22, 2	2011-02-22
Method for forming a shallow junction region using defect engineering and laser annealing Grant 7,888,224 - Ong , et al. February 15, 2	2011-02-15
Strained Channel Transistor And Method Of Fabrication Thereof App 20100320503 - Chong; Yung Fu ; et al.	2010-12-23
Semiconductor Devices Having pFET with SiGe Gate Electrode and Embedded SiGe Source/Drain Regions and Methods of Making the Same App 20100297818 - Han; Jin-Ping ; et al.	2010-11-25
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same Grant 7,800,182 - Han , et al. September 21, 2	2010-09-21
Formation Of Raised Source/drain Stuctures In Nfet With Embedded Sige In Pfet App 20100219485 - CHONG; Yung Fu ; et al.	2010-09-02
Strained channel transistor and method of fabrication thereof Grant 7,772,071 - Chong , et al. August 10, 2	2010-08-10
Method For Forming A Shallow Junction Region Using Defect Engineering And Laser Annealing App 20100124809 - Ong; Kuang Kian ; et al.	2010-05-20
Formation of raised source/drain structures in NFET with embedded SiGe in PFET Grant 7,718,500 - Chong , et al. May 18, 2	2010-05-18
Integrated circuit system employing a condensation process Grant 7,692,213 - Teo , et al. April 6, 2	2010-04-06
Method to fabricate variable work function gates for FUSI devices Grant 7,645,687 - Chong , et al. January 12, 2	2010-01-12
Diffusion Barrier And Method Of Formation Thereof App 20090315152 - TAN; Shyue Seng ; et al.	2009-12-24
Gate stress engineering for MOSFET Grant 7,595,233 - Luo , et al. September 29, 2	2009-09-29
Method to form selective strained Si using lateral epitaxy Grant 7,572,712 - Chong , et al. August 11, 2	2009-08-11
Method of manufacturing a semiconductor structure Grant 7,566,609 - Luo , et al. July 28, 2	2009-07-28
Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module App 20090184341 - Chong; Yung Fu ; et al.	2009-07-23
Integrated Circuit System Employing A Condensation Process App 20090039388 - Teo; Lee Wee ; et al.	2009-02-12
Method and structure to form self-aligned selective-SOI Grant 7,482,656 - Luo , et al. January 27, 2	2009-01-27
Methods Of Stressing Transistor Channel With Replaced Gate App 20080286916 - Luo; Zhijiong ; et al.	2008-11-20
Substantially L-shaped Silicide For Contact And Related Method App 20080283934 - Luo; Zhijiong ; et al.	2008-11-20
Method of forming substantially L-shaped silicide contact for a semiconductor device Grant 7,442,619 - Luo , et al. October 28, 2	2008-10-28
Method to engineer etch profiles in Si substrate for advanced semiconductor devices Grant 7,442,618 - Chong , et al. October 28, 2	2008-10-28
Method of fabricating a transistor structure Grant 7,413,961 - Chong , et al. August 19, 2	2008-08-19
Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor Grant 7,405,131 - Chong , et al. July 29, 2	2008-07-29
Integrated Circuit System Employing Differential Spacers App 20080142879 - Chong; Yung Fu ; et al.	2008-06-19
Method To Form Selective Strained Si Using Lateral Epitaxy App 20080116482 - Chong; Yung Fu ; et al.	2008-05-22
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same App 20080119019 - Han; Jin-Ping ; et al.	2008-05-22
Semiconductor Device With Doped Transistor App 20080087958 - Verma; Purakh Raj ; et al.	2008-04-17
Semiconductor System Using Germanium Condensation App 20080042209 - Tan; Shyue Seng ; et al.	2008-02-21
Semiconductor device and fabrication method Grant 7,326,609 - Verma , et al. February 5, 2	2008-02-05
BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT App 20080023752 - Chen; Xiangdong ; et al.	2008-01-31
Semiconductor Structure Including Isolation Region With Variable Linewidth And Method For Fabrication Therof App 20070293016 - Luo; Zhijiong ; et al.	2007-12-20
Methods Of Stressing Transistor Channel With Replaced Gate And Related Structures App 20070281405 - Luo; Zhijiong ; et al.	2007-12-06
Method And Structure To Form Self-aligned Selective-soi App 20070278591 - Luo; Zhijiong ; et al.	2007-12-06
Gate Stress Engineering For Mosfet App 20070278583 - Luo; Zhijiong ; et al.	2007-12-06
Substantially L-shaped Silicide For Contact And Related Method App 20070267753 - Luo; Zhijiong ; et al.	2007-11-22
Strained Channel Transistor And Method Of Fabrication Thereof App 20070267703 - Chong; Yung Fu ; et al.	2007-11-22
Method Of Fabricating A Transistor Structure App 20070269952 - Chong; Yung Fu ; et al.	2007-11-22
Method to control source/drain stressor profiles for stress engineering App 20070235802 - Chong; Yung Fu ; et al.	2007-10-11
Integrated circuit isolation system App 20070205469 - Chong; Yung Fu ; et al.	2007-09-06
Laser activation of implanted contact plug for memory bitline fabrication Grant 7,256,112 - Chong , et al. August 14, 2	2007-08-14
Formation of raised source/drain structures in NFET with embedded SiGe in PFET App 20070138570 - Chong; Yung Fu ; et al.	2007-06-21
Embedded stressor structure and process App 20070132038 - Chong; Yung Fu ; et al.	2007-06-14
Method Of Manufacturing A Semiconductor Structure App 20070122955 - Luo; Zhijiong ; et al.	2007-05-31
Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing App 20070032026 - Ong; Kuang Kian ; et al.	2007-02-08
Method to engineer etch profiles in Si substrate for advanced semiconductor devices App 20070020861 - Chong; Yung Fu ; et al.	2007-01-25
Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor App 20070020864 - Chong; Yung Fu ; et al.	2007-01-25
Semiconductor Device And Fabrication Method App 20060252188 - Verma; Purakh Raj ; et al.	2006-11-09
Method to fabricate variable work function gates for FUSI devices App 20060160290 - Chong; Yung Fu ; et al.	2006-07-20
Laser activation of implanted contact plug for memory bitline fabrication App 20060160343 - Chong; Yung Fu ; et al.	2006-07-20
Method for engineering hybrid orientation/material semiconductor substrate App 20060105533 - Chong; Yung Fu ; et al.	2006-05-18
Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure Grant 6,734,072 - Chong , et al. May 11, 2	2004-05-11
Method to fabricate elevated source/drain structures in MOS transistors Grant 6,727,151 - Chong , et al. April 27, 2	2004-04-27
Method To Fabricate Elevated Source/drain Structures In Mos Transistors App 20040029320 - Chong, Yung Fu ; et al.	2004-02-12
Formation of silicided shallow junctions using implant through metal technology and laser annealing process Grant 6,624,489 - Chong , et al. September 23, 2	2003-09-23
Method of fabricating short channel MOS transistors with source/drain extensions Grant 6,566,215 - Chong , et al. May 20, 2	2003-05-20
Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure Grant 6,534,390 - Chong , et al. March 18, 2	2003-03-18
Formation of silicided shallow junctions using implant through metal technology and laser annealing process App 20020098689 - Chong, Yung Fu ; et al.	2002-07-25
Activating source and drain junctions and extensions using a single laser anneal Grant 6,391,731 - Chong , et al. May 21, 2	2002-05-21
Method to reduce polysilicon depletion in MOS transistors Grant 6,387,784 - Chong , et al. May 14, 2	2002-05-14
Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Grant 6,365,446 - Chong , et al. April 2, 2	2002-04-02
Method to form MOS transistors with shallow junctions using laser annealing Grant 6,335,253 - Chong , et al. January 1, 2	2002-01-01

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