Chong; Nui
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chong; Nui.The latest application filed is for "integrated circuit die with in-chip heat sink".
- Chong; Nui - San Jose CA
- Chong; Nui - Cupertino CA
| Patent | Date |
|---|---|
| Warpage reduction Grant 11,164,749 - Chong , et al. November 2, 2 | 2021-11-02 |
| Testing of bonded wafers and structures for testing bonded wafers Grant 11,119,146 - Chong , et al. September 14, 2 | 2021-09-14 |
| IC die with dummy structures Grant 11,114,344 - Lin , et al. September 7, 2 | 2021-09-07 |
| Test circuits for testing a die stack Grant 11,054,461 - Chong , et al. July 6, 2 | 2021-07-06 |
| Integrated circuit skew determination Grant 10,756,711 - Majumdar , et al. A | 2020-08-25 |
| Chip package assembly with modular core dice Grant 10,692,837 - Kim , et al. | 2020-06-23 |
| Integrated circuit die with in-chip heat sink Grant 10,629,512 - Pan , et al. | 2020-04-21 |
| Selectively disconnecting a memory cell from a power supply Grant 10,566,050 - Zhou , et al. Feb | 2020-02-18 |
| Integrated Circuit Die With In-chip Heat Sink App 20200006186 - Pan; Hong-Tsz ; et al. | 2020-01-02 |
| In-die transistor characterization in an IC Grant 10,379,155 - Yeh , et al. A | 2019-08-13 |
| Method and design of low sheet resistance MEOL resistors Grant 10,103,139 - Chong , et al. October 16, 2 | 2018-10-16 |
| Using an integrated circuit die for multiple devices Grant 10,043,724 - Gaide , et al. August 7, 2 | 2018-08-07 |
| Method And Design Of Low Sheet Resistance Meol Resistors App 20170012041 - Chong; Nui ; et al. | 2017-01-12 |
| In-die Transistor Characterization In An Ic App 20160097805 - Yeh; Ping-Chin ; et al. | 2016-04-07 |
| Two gate pitch FPGA memory cell Grant 9,177,634 - Young , et al. November 3, 2 | 2015-11-03 |
| Systems and methods for electrostatic discharge protection Grant 8,194,372 - Chong , et al. June 5, 2 | 2012-06-05 |
| Embedded inductor Grant 8,068,004 - Chong , et al. November 29, 2 | 2011-11-29 |
| Method and apparatus for compensating an integrated circuit layout for mechanical stress effects Grant 7,673,270 - Wang , et al. March 2, 2 | 2010-03-02 |
| High-voltage protection device and process Grant 7,307,319 - Chong , et al. December 11, 2 | 2007-12-11 |
| Metal junction diode and process App 20060157748 - Chong; Nui ; et al. | 2006-07-20 |
| Diode with low junction capacitance App 20060125014 - Chong; Nui ; et al. | 2006-06-15 |
| Electrostatic discharge simulation Grant 7,024,646 - Logie , et al. April 4, 2 | 2006-04-04 |
| Electrostatic discharge protection circuits App 20050213271 - Chong, Nui ; et al. | 2005-09-29 |
| Electrostatic discharge simulation App 20050172246 - Logie, Stewart ; et al. | 2005-08-04 |
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