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Patent applications and USPTO patent grants for Chong; Kwen Siong.The latest application filed is for "circuit arrangements and methods for forming the same".
Patent | Date |
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Circuit arrangements and methods for forming the same Grant 11,356,094 - Chang , et al. June 7, 2 | 2022-06-07 |
Hardware security to countermeasure side-channel attacks Grant 11,227,071 - Chong , et al. January 18, 2 | 2022-01-18 |
Circuit, method for sizing an aspect ratio of transistors of a circuit, and circuit arrangement Grant 11,177,807 - Chang , et al. November 16, 2 | 2021-11-16 |
Circuit Arrangements And Methods For Forming The Same App 20210083665 - Chang; Joseph Sylvester ;   et al. | 2021-03-18 |
Circuit, Method For Sizing An Aspect Ratio Of Transistors Of A Circuit, And Circuit Arrangement App 20210058083 - CHANG; Joseph Sylvester ;   et al. | 2021-02-25 |
Circuit and method of forming the same Grant 10,930,646 - Chang , et al. February 23, 2 | 2021-02-23 |
Integrated Circuit Layout Cell, Integrated Circuit Layout Arrangement, And Methods Of Forming The Same App 20210050351 - CHONG; Kwen Siong ;   et al. | 2021-02-18 |
Circuit And Method Of Forming The Same App 20200126971 - Chang; Joseph Sylvester ;   et al. | 2020-04-23 |
Hardware Security To Countermeasure Side-channel Attacks App 20200004992 - CHONG; Kwen Siong ;   et al. | 2020-01-02 |
Digital cell Grant 8,994,406 - Chang , et al. March 31, 2 | 2015-03-31 |
Asynchronous-logic circuit for full dynamic voltage control Grant 8,791,717 - Chang , et al. July 29, 2 | 2014-07-29 |
Digital Cell App 20130342253 - Chang; Joseph Sylvester ;   et al. | 2013-12-26 |
Asynchronous-logic Circuit For Full Dynamic Voltage Control App 20130113522 - Chang; Joseph Sylvester ;   et al. | 2013-05-09 |
Digital multiplier with reduced spurious switching by means of Latch Adders Grant 7,206,801 - Chang , et al. April 17, 2 | 2007-04-17 |
Digital Multiplier with reduced spurious switching by means of Latch Adders App 20030220957 - Chang, Joseph Sylvester ;   et al. | 2003-11-27 |
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