loadpatents
name:-0.031825065612793
name:-0.02610182762146
name:-0.067860126495361
Choi; Youn Sung Patent Filings

Choi; Youn Sung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Choi; Youn Sung.The latest application filed is for "gate-to-contact short prevention with an inner spacer".

Company Profile
8.28.31
  • Choi; Youn Sung - San Diego CA
  • Choi; Youn Sung - Allen TX
  • Choi; Youn Sung - Plano TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Leakage current reduction in polysilicon-on-active-edge structures
Grant 11,444,201 - Choi , et al. September 13, 2
2022-09-13
Gate-to-contact Short Prevention With An Inner Spacer
App 20220216328 - SUH; Youseok ;   et al.
2022-07-07
Leakage Current Reduction In Polysilicon-on-active-edge Structures
App 20210305429 - CHOI; Youn Sung ;   et al.
2021-09-30
SRAM source-drain structure
Grant 11,075,206 - Lim , et al. July 27, 2
2021-07-27
Fin Field-effect Transistor (fet) (finfet) Circuits Employing Replacement N-type Fet (nfet) Source/drain (s/d) To Avoid Or Prevent Short Defects And Related Methods Of Fabrication
App 20210143153 - Lim; Kwanyong ;   et al.
2021-05-13
Sensor for gate leakage detection
Grant 10,996,261 - Park , et al. May 4, 2
2021-05-04
Integration of finFET device
Grant 10,950,488 - Kim , et al. March 16, 2
2021-03-16
Inline Monitoring Test Structure
App 20200256915 - A1
2020-08-13
Sram Source-drain Structure
App 20200194440 - LIM; Kwanyong ;   et al.
2020-06-18
Systems and methods for fabrication of gated diodes with selective epitaxial growth
Grant 10,600,774 - Choi , et al.
2020-03-24
Sensor For Gate Leakage Detection
App 20200049757 - PARK; Hyunwoo ;   et al.
2020-02-13
Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells
Grant 10,490,558 - Choi , et al. Nov
2019-11-26
Systems And Methods For Fabrication Of Gated Diodes With Selective Epitaxial Growth
App 20190312025 - Choi; Youn Sung ;   et al.
2019-10-10
Integration Of Finfet Device
App 20190273013 - KIM; Ryoung-han ;   et al.
2019-09-05
Reducing Or Avoiding Mechanical Stress In Static Random Access Memory (sram) Strap Cells
App 20180350819 - Choi; Youn Sung ;   et al.
2018-12-06
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
Grant 10,062,768 - Choi , et al. August 28, 2
2018-08-28
Integrated circuit with dual stress liner boundary
Grant 9,953,967 - Choi , et al. April 24, 2
2018-04-24
Design And Integration Of Finfet Device
App 20180108564 - KIM; Ryoung-han ;   et al.
2018-04-19
Integration of analog transistor
Grant 9,922,971 - Pal , et al. March 20, 2
2018-03-20
Field-effect Transistor (fet) Devices Employing Adjacent Asymmetric Active Gate / Dummy Gate Width Layout
App 20180061943 - Choi; Youn Sung ;   et al.
2018-03-01
Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions
Grant 9,882,051 - Roh , et al. January 30, 2
2018-01-30
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
Grant 9,634,138 - Choi , et al. April 25, 2
2017-04-25
Integrated Circuit With Dual Stress Liner Boundary
App 20170084598 - Choi; Youn Sung ;   et al.
2017-03-23
Integrated circuit with dual stress liner boundary
Grant 9,543,437 - Choi , et al. January 10, 2
2017-01-10
Integration Of Analog Transistor
App 20160322352 - PAL; Himadri Sekhar ;   et al.
2016-11-03
Integration of analog transistor
Grant 9,412,741 - Pal , et al. August 9, 2
2016-08-09
Silicide formation due to improved SiGe faceting
Grant 9,406,769 - Ekbote , et al. August 2, 2
2016-08-02
Integration Of Analog Transistor
App 20160043076 - PAL; Himadri Sekhar ;   et al.
2016-02-11
SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING
App 20160027888 - EKBOTE; Shashank S. ;   et al.
2016-01-28
Integrated Circuit With Dual Stress Liner Boundary
App 20160013314 - Choi; Youn Sung ;   et al.
2016-01-14
Integration of analog transistor
Grant 9,202,810 - Pal , et al. December 1, 2
2015-12-01
Silicide formation due to improved SiGe faceting
Grant 9,202,883 - Ekbote , et al. December 1, 2
2015-12-01
Method for improving device performance using dual stress liner boundary
Grant 9,171,901 - Choi , et al. October 27, 2
2015-10-27
Silicide Formation Due To Improved Sige Faceting
App 20150287801 - EKBOTE; Shashank S. ;   et al.
2015-10-08
Integration Of Analog Transistor
App 20150287717 - PAL; Himadri Sekhar ;   et al.
2015-10-08
Silicide formation due to improved SiGe faceting
Grant 9,093,298 - Ekbote , et al. July 28, 2
2015-07-28
Design And Integration Of Finfet Device
App 20150171217 - KIM; Ryoung-han ;   et al.
2015-06-18
Method of printing multiple structure widths using spacer double patterning
Grant 9,029,263 - Kim , et al. May 12, 2
2015-05-12
Drain induced barrier lowering with anti-punch-through implant
Grant 8,987,748 - Pal , et al. March 24, 2
2015-03-24
SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING
App 20150054084 - EKBOTE; Shashank S. ;   et al.
2015-02-26
Method For Improving Device Performance Using Dual Stress Liner Boundary
App 20140374836 - CHOI; Youn Sung ;   et al.
2014-12-25
Method for improving device performance using dual stress liner boundary
Grant 8,859,357 - Choi , et al. October 14, 2
2014-10-14
Integrated circuit having silicide block resistor
Grant 8,748,256 - Zhao , et al. June 10, 2
2014-06-10
Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices
Grant 8,669,775 - Choi , et al. March 11, 2
2014-03-11
On-die parametric test modules for in-line monitoring of context dependent effects
Grant 8,664,968 - Baldwin , et al. March 4, 2
2014-03-04
Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions
App 20140054710 - Choi; Youn Sung ;   et al.
2014-02-27
Integrated Circuit (ic) Having Tsvs And Stress Compensating Layer
App 20130249011 - CHOI; YOUN SUNG ;   et al.
2013-09-26
Integrated Circuit Having Silicide Block Resistor
App 20130200466 - ZHAO; SONG ;   et al.
2013-08-08
Drain Induced Barrier Lowering With Anti-punch-through Implant
App 20130161639 - PAL; Himadri Sekhar ;   et al.
2013-06-27
Method For Improving Device Performance Using Dual Stress Liner Boundary
App 20120119301 - Choi; Youn Sung ;   et al.
2012-05-17
SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES
App 20120074980 - Choi; Youn Sung ;   et al.
2012-03-29
On-die Parametric Test Modules For In-line Monitoring Of Context Dependent Effects
App 20120074973 - Baldwin; Gregory Charles ;   et al.
2012-03-29

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