CHOI; Soo Han

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHOI; Soo Han.The latest application filed is for "system and method for synchronizing net text across hierarchical levels".

Company Profile

1.13.12

CHOI; Soo Han - Mountain View CA
Choi; Soo Han - Pleasanton CA
Choi; Soo-Han - Seoul KR
Choi; Soo-Han - Kyungki-do KR
Choi; Soo-Han - Suwon KR
Choi, Soo-Han - Suwon-city KR
Choi; Soo Han - Bubaleub KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and Method for Synchronizing Net Text Across Hierarchical Levels App 20210390244 - SCHAFFER; Louis ; et al.	2021-12-16
System And Method For Providing Enhanced Net Pruning App 20210374321 - Schaffer; Louis ; et al.	2021-12-02
Categorized stitching guidance for triple-patterning technology Grant 10,261,412 - Choi , et al.	2019-04-16
Categorized Stitching Guidance For Triple-patterning Technology App 20170336707 - CHOI; Soo Han ; et al.	2017-11-23
Categorized stitching guidance for triple-patterning technology Grant 9,747,407 - Choi , et al. August 29, 2	2017-08-29
Methods of generating circuit layouts that are to be manufactured using SADP routing techniques Grant 9,613,177 - Yuan , et al. April 4, 2	2017-04-04
Color-insensitive rules for routing structures Grant 9,400,863 - Yuan , et al. July 26, 2	2016-07-26
Color-insensitive rules for routing structures Grant 9,158,879 - Yuan , et al. October 13, 2	2015-10-13
Categorized Stitching Guidance For Triple-patterning Technology App 20150286771 - CHOI; Soo Han ; et al.	2015-10-08
Method of forming a pattern Grant 9,141,751 - Lee , et al. September 22, 2	2015-09-22
Color-insensitive Rules For Routing Structures App 20150220676 - YUAN; Lei ; et al.	2015-08-06
Methods Of Generating Circuit Layouts That Are To Be Manufactured Using Sadp Routing Techniques App 20150113484 - Yuan; Lei ; et al.	2015-04-23
Color-insensitive Rules For Routing Structures App 20150067633 - YUAN; Lei ; et al.	2015-03-05
Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process Grant 8,969,199 - Yuan , et al. March 3, 2	2015-03-03
Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules Grant 8,954,913 - Yuan , et al. February 10, 2	2015-02-10
Method Of Forming A Pattern App 20140162460 - LEE; HYUN-JONG ; et al.	2014-06-12
System for analyzing mask topography and method of forming image using the system Grant 8,045,787 - Choi , et al. October 25, 2	2011-10-25
System for analyzing mask topography and method of forming image using the system App 20080175432 - Choi; Soo-han ; et al.	2008-07-24
Method of creating a layout of a set of masks Grant 7,361,435 - Park , et al. April 22, 2	2008-04-22
Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereof Grant 7,097,949 - Kim , et al. August 29, 2	2006-08-29
Mask used in manufacturing highly-integrated circuit device, method of creating layout thereof, manufacturing method thereof, and manufacturing method for highly-integrated circuit device using the same App 20060099522 - Park; Chul-Hong ; et al.	2006-05-11
Mask for manufacturing a highly-integrated circuit device Grant 6,998,199 - Park , et al. February 14, 2	2006-02-14
Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereof App 20040091794 - Kim, Dong-Hyun ; et al.	2004-05-13
Mask used in manufacturing highly-integrated circuit device, method of creating layout thereof, manufacturing method thereof, and manufacturing method for highly-integrated circuit device using the same App 20040043305 - Park, Chul-Hong ; et al.	2004-03-04
Hot-wall CVD method for forming a ferroelectric film Grant 5,827,571 - Lee , et al. October 27, 1	1998-10-27

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