Choi; Seungmoo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Choi; Seungmoo.The latest application filed is for "method of forming controllably conductive oxide".

Company Profile

1.21.11

Choi; Seungmoo - Newport Beach CA
Choi; Seungmoo - Macungie PA
Choi; Seungmoo - Allentown PA
Choi; Seungmoo - Orlando FL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming controllably conductive oxide Grant 10,147,877 - Buynoski , et al. De	2018-12-04
Resistive memory array using P-I-N diode select device and methods of fabrication thereof Grant 9,837,469 - Choi , et al. December 5, 2	2017-12-05
Method of forming controllably conductive oxide App 20160380195 - BUYNOSKI; Matthew ; et al.	2016-12-29
Resistive memory array using P-I-N diode select device and methods of fabrication thereof Grant 9,490,126 - Choi , et al. November 8, 2	2016-11-08
Method of forming controllably conductive oxide Grant 9,461,247 - Buynoski , et al. October 4, 2	2016-10-04
Method Of Forming Controllably Conductive Oxide App 20150144857 - BUYNOSKI; Matthew ; et al.	2015-05-28
Method of forming controllably conductive oxide Grant 8,946,020 - Buynoski , et al. February 3, 2	2015-02-03
Resistive Memory Array Using P-i-n Diode Select Device And Methods Of Fabrication Thereof App 20110253968 - CHOI; Seungmoo ; et al.	2011-10-20
Resistive memory array using P-I-N diode select device and methods of fabrication thereof Grant 7,989,328 - Choi , et al. August 2, 2	2011-08-02
Integrated circuit with a trench capacitor structure and method of manufacture Grant 7,563,669 - Chittipeddi , et al. July 21, 2	2009-07-21
Method of forming controllably conductive oxide App 20090067213 - Buynoski; Matthew ; et al.	2009-03-12
Resistive memory array using P-I-N diode select device and methods of fabrication thereof App 20080144354 - Choi; Seungmoo ; et al.	2008-06-19
Integrated Circuit With A Trench Capacitor Structure And Method Of Manufacture App 20070267670 - Chittipeddi; Sailesh ; et al.	2007-11-22
Device having active regions of different depths App 20070099372 - Chittipeddi; Sailesh ; et al.	2007-05-03
Multiple purpose reticle layout for selective printing of test circuits Grant 6,893,806 - Bollinger , et al. May 17, 2	2005-05-17
Method of fabricating a silicon on insulator transistor structure for imbedded DRAM Grant 6,890,827 - Choi , et al. May 10, 2	2005-05-10
Method for fabricating MOS device with halo implanted region Grant 6,762,459 - Choi , et al. July 13, 2	2004-07-13
Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method Grant 6,603,168 - Choi August 5, 2	2003-08-05
Multiple purpose reticle layout for selective printing of test circuits App 20030039928 - Bollinger, Cheryl Anne ; et al.	2003-02-27
Device and method for forming semiconductor interconnections in an integrated circuit substrate Grant 6,503,787 - Choi January 7, 2	2003-01-07
Contactless local interconnect process utilizing self-aligned silicide Grant 6,468,899 - Choi October 22, 2	2002-10-22
Method for fabricating MOS device with halo implanted region App 20020055212 - Choi, Seungmoo ; et al.	2002-05-09
Silicon on insulator transistor structure for imbedded DRAM App 20020019096 - Choi, Seungmoo ; et al.	2002-02-14
Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same Grant 6,340,827 - Choi , et al. January 22, 2	2002-01-22
Semiconductor Device Having Self-aligned Contact And Landing Pad Structure And Method Of Forming Same App 20020000601 - CHOI, SEUNGMOO	2002-01-03
Integrated circuit device having dual damascene capacitor Grant 6,320,244 - Alers , et al. November 20, 2	2001-11-20
Method for making a semiconductor device Grant 6,274,409 - Choi August 14, 2	2001-08-14
Device and method for forming semiconductor interconnections in an integrated circuit substrate Grant 6,215,158 - Choi April 10, 2	2001-04-10
DRAM capacitor including Cu plug and Ta barrier and method of forming Grant 6,168,991 - Choi , et al. January 2, 2	2001-01-02
Integrate DRAM cell having a DRAM capacitor and a transistor Grant 6,072,210 - Choi June 6, 2	2000-06-06

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