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HTO offset for long Leffective, better device performance
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HTO offset and BL trench process for memory device to improve device performance
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Gate Trim Process Using Either Wet Etch Or Dry Etch Approach To Target Cd For Selected Transistors
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Hto Offset And Bl Trench Process For Memory Device To Improve Device Performance
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HTO offset and BL trench process for memory device to improve device performance
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Wordline Resistance Reduction Method And Structure In An Integrated Circuit Memory Device
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Wordline resistance reduction method and structure in an integrated circuit memory device
Grant 7,867,899 - Fang , et al. January 11, 2 | 2011-01-11 |
Gate Trim Process Using Either Wet Etch Or Dry Etch Appraoch To Target Cd For Selected Transistors
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Self-aligned Patterning Method By Using Non-conformal Film And Etch For Flash Memory And Other Semiconductor Applications
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Dual storage node memory devices and methods for fabricating the same
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Hto Offset And Bl Trench Process For Memory Device To Improve Device Performance
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Hto Offset For Long Leffective, Better Device Performance
App 20100155817 - Cheng; Ning ; et al. | 2010-06-24 |
Hto Offset Spacers And Dip Off Process To Define Junction
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Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
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Memory Device Etch Methods
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Memory device etch methods
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Wordline Resistance Reduction Method And Structure In An Integrated Circuit Memory Device
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Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
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Memory Device Etch Methods
App 20080153298 - Hui; Angela T. ; et al. | 2008-06-26 |
Dual Storage Node Memory Devices And Methods For Fabricating The Same
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