loadpatents
name:-0.013720989227295
name:-0.015489101409912
name:-0.30464887619019
CHOI; Eun Yeoung Patent Filings

CHOI; Eun Yeoung

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHOI; Eun Yeoung.The latest application filed is for "three dimensional semiconductor device and method of manufacturing the same".

Company Profile
6.11.13
  • CHOI; Eun Yeoung - Suwon-si KR
  • CHOI; Eun Yeoung - Hwaseong-si KR
  • Choi; Eun-Yeoung - Seoul N/A KR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Three Dimensional Semiconductor Device And Method Of Manufacturing The Same
App 20220093642 - CHOI; Eun Yeoung ;   et al.
2022-03-24
Vertical-type Memory Device
App 20220028889 - CHOI; Eun Yeoung ;   et al.
2022-01-27
Three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns and method of manufacturing the same
Grant 11,201,166 - Choi , et al. December 14, 2
2021-12-14
Vertical-type memory device
Grant 11,164,884 - Choi , et al. November 2, 2
2021-11-02
Method of manufacturing semiconductor device
Grant 11,094,709 - Choi , et al. August 17, 2
2021-08-17
Three Dimensional Semiconductor Device And Method Of Manufacturing The Same
App 20200381446 - CHOI; Eun Yeoung ;   et al.
2020-12-03
Vertical-type Memory Device
App 20200144284 - Choi; Eun Yeoung ;   et al.
2020-05-07
Method Of Manufacturing Semiconductor Device
App 20200135759 - CHOI; Eun Yeoung ;   et al.
2020-04-30
Semiconductor device including a dielectric layer
Grant 10,559,584 - Choi , et al. Feb
2020-02-11
Semiconductor device
Grant 10,355,099 - Choi , et al. July 16, 2
2019-07-16
Semiconductor Device
App 20180366554 - CHOI; Eun Yeoung ;   et al.
2018-12-20
Semiconductor Device Including a Dielectric Layer
App 20180012902 - Choi; Eun Yeoung ;   et al.
2018-01-11
Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same
Grant 9,698,233 - Choi , et al. July 4, 2
2017-07-04
Methods of manufacturing semiconductor devices including an oxide layer
Grant 9,613,800 - Go , et al. April 4, 2
2017-04-04
Method for manufacturing semiconductor device
Grant 9,490,140 - Go , et al. November 8, 2
2016-11-08
Method For Manufacturing Semiconductor Device
App 20160064227 - GO; Hyun Yong ;   et al.
2016-03-03
Tunnel Insulation Layer Structures, Methods Of Manufacturing The Same, And Vertical Memory Devices Including The Same
App 20150279955 - CHOI; Eun-Yeoung ;   et al.
2015-10-01
Methods Of Manufacturing Semiconductor Devices Including An Oxide Layer
App 20150235836 - GO; Hyun-Yong ;   et al.
2015-08-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed