Choe; Kok Heng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Choe; Kok Heng.The latest application filed is for "systems and methods for configuring an sopc without a need to use an external memory".

Company Profile

0.24.4

Choe; Kok Heng - Sg Ara MY
Choe; Kok Heng - Bayan Lepas MY
Choe; Kok Heng - Penang N/A MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interface for efficient usage of communication circuitry Grant 10,536,174 - Choe Ja	2020-01-14
Systems and methods for configuring an SOPC without a need to use an external memory Grant 9,912,337 - Hooi , et al. March 6, 2	2018-03-06
Systems And Methods For Configuring An SOPC Without A Need To Use An External Memory App 20170117899 - Hooi; Woi Jie ; et al.	2017-04-27
Systems and methods for configuring an SOPC without a need to use an external memory Grant 9,543,956 - Hooi , et al. January 10, 2	2017-01-10
FPGA equivalent input and output grid muxing on structural ASIC memory Grant 9,275,694 - Choe March 1, 2	2016-03-01
Configuring a programmable logic device using a configuration bit stream without phantom bits Grant 9,130,561 - Choe September 8, 2	2015-09-08
Configuring a programmable logic device using a configuration bit stream without phantom bits Grant 8,910,102 - Choe December 9, 2	2014-12-09
RAM/ROM memory circuit Grant 8,885,392 - Choe November 11, 2	2014-11-11
Configuring A Programmable Logic Device Using A Configuration Bit Stream Without Phantom Bits App 20140245246 - Choe; Kok Heng	2014-08-28
Multiplier-accumulator circuitry and methods Grant 8,645,450 - Choe , et al. February 4, 2	2014-02-04
Systems And Methods For Configuring An Sopc Without A Need To Use An External Memory App 20120286821 - Hooi; Woi Jie ; et al.	2012-11-15
Real time feedback compensation of programmable logic memory Grant 8,261,141 - Choe , et al. September 4, 2	2012-09-04
FPGA equivalent input and output grid muxing on structural ASIC memory Grant 7,901,999 - Choe March 8, 2	2011-03-08
Real time feedback compensation of programmable logic memory Grant 7,882,408 - Choe , et al. February 1, 2	2011-02-01
Dual port random-access-memory circuitry Grant RE41,325 - Yu , et al. May 11, 2	2010-05-11
Techniques for precision biasing output driver for a calibrated on-chip termination circuit Grant 7,679,397 - Kok , et al. March 16, 2	2010-03-16
Distributed memory circuitry on structured application-specific integrated circuit devices Grant 7,586,327 - Choe , et al. September 8, 2	2009-09-08
FPGA equivalent input and output grid muxing on structural ASIC memory Grant 7,542,324 - Choe June 2, 2	2009-06-02
Dual port random-access-memory circuitry Grant 7,471,588 - Yu , et al. December 30, 2	2008-12-30
Programmable logic device memory blocks with adjustable timing Grant 7,319,619 - Choe January 15, 2	2008-01-15
Dual port random-access-memory circuitry App 20070258313 - Yu; Haiming ; et al.	2007-11-08
Real time feedback compensation of programmable logic memory Grant 7,164,289 - Choe , et al. January 16, 2	2007-01-16
Programmable Logic with Pipelined Memory Operation Grant 7,071,731 - Choe , et al. July 4, 2	2006-07-04
Voltage-based timing control of memory bit lines Grant 7,046,566 - Choe , et al. May 16, 2	2006-05-16

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