Cho; Sung-We

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cho; Sung-We.The latest application filed is for "integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped ".

Company Profile

3.13.12

Cho; Sung-We - Hwaseong-si KR
Cho; Sung-we - Seoul KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Scan flip-flop and scan test circuit including the same Grant 11,287,474 - Kim , et al. March 29, 2	2022-03-29
Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration Grant 11,189,639 - Kim , et al. November 30, 2	2021-11-30
Standard cell for removing routing interference between adjacent pins and device including the same Grant 11,031,385 - Seo , et al. June 8, 2	2021-06-08
Integrated circuits including standard cells and methods of manufacturing the integrated circuits Grant 10,990,740 - Kim , et al. April 27, 2	2021-04-27
Integrated Circuit Including Interconnection And Method Of Fabricating The Same, The Interconnection Including A Pattern Shaped App 20200235126 - KIM; Ha-young ; et al.	2020-07-23
Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration Grant 10,651,201 - Kim , et al.	2020-05-12
Standard Cell For Removing Routing Interference Between Adjacent Pins And Device Including The Same App 20200126968 - SEO; Jae-Woo ; et al.	2020-04-23
Integrated Circuits Including Standard Cells And Methods Of Manufacturing The Integrated Circuits App 20200050728 - KIM; JIN-TAE ; et al.	2020-02-13
Standard cell for removing routing interference between adjacent pins and device including the same Grant 10,553,574 - Seo , et al. Fe	2020-02-04
Integrated circuit and method of designing integrated circuit Grant 10,216,883 - Kim , et al. Feb	2019-02-26
Integrated Circuit Including Interconnection For Mitigating Electromigration And Method Of Fabricating The Same App 20180294280 - KIM; Ha-young ; et al.	2018-10-11
Integrated circuit and semiconductor device Grant 9,905,561 - Kim , et al. February 27, 2	2018-02-27
Standard Cell For Removing Routing Interference Between Adjacent Pins And Device Including The Same App 20170294430 - SEO; Jae-Woo ; et al.	2017-10-12
Integrated Circuit And Method Of Designing Integrated Circuit App 20170277819 - KIM; HA-YOUNG ; et al.	2017-09-28
Method and program for designing integrated circuit Grant 9,665,678 - Cho , et al. May 30, 2	2017-05-30
Integrated Circuit And Semiconductor Device App 20170133380 - KIM; Ha-young ; et al.	2017-05-11
Integrated circuit and semiconductor device Grant 9,583,493 - Kim , et al. February 28, 2	2017-02-28
Integrated Circuit And Semiconductor Device App 20160300839 - Kim; Ha-young ; et al.	2016-10-13
Method And Program For Designing Integrated Circuit App 20160034627 - Cho; Sung-we ; et al.	2016-02-04
Clocked state devices including master-slave terminal transmission gates and methods of operating same Grant 7,301,381 - Rhee , et al. November 27, 2	2007-11-27
Clocked state devices including master-slave terminal transmission gates and methods of operating same App 20060103443 - Rhee; Young-chul ; et al.	2006-05-18
MTCMOS flip-flop circuit capable of retaining data in sleep mode Grant 6,870,412 - Cho March 22, 2	2005-03-22
MTCMOS flip-flop circuit capable of retaining data in sleep mode App 20040090256 - Cho, Sung-We	2004-05-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.