Cho; Myoung Kwan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cho; Myoung Kwan.The latest application filed is for "semiconductor memory device and operation method thereof".

Company Profile

0.12.8

Cho; Myoung Kwan - Gyeonggi-do KR
Cho; Myoung Kwan - Seongnam-si KR
Cho; Myoung-Kwan - Gyeongsangbuk-do KR
Cho; Myoung-kwan - Gyungsangbuk-do KR
Cho; Myoung-kwan - Kyungki-do KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory device with control logic configured to group memory blocks, and determine driving voltages to be respectively applied to the groups to control memory operation Grant 10,418,116 - Park , et al. Sept	2019-09-17
Semiconductor memory device and operation method thereof Grant 10,224,102 - Choi , et al.	2019-03-05
Semiconductor Memory Device And Operation Method Thereof App 20180336949 - CHOI; Gil Bok ; et al.	2018-11-22
Semiconductor Memory Device And Operating Method Thereof App 20180082752 - PARK; Min Sang ; et al.	2018-03-22
Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same Grant 7,547,943 - Cho , et al. June 16, 2	2009-06-16
Methods of fabricating integrated circuit devices having contact holes exposing gate electrodes in active regions Grant 7,320,909 - Park , et al. January 22, 2	2008-01-22
Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels Grant 7,315,055 - Cho , et al. January 1, 2	2008-01-01
Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same App 20060141715 - Park; Jeung-Hwan ; et al.	2006-06-29
Integrated circuit devices having contact holes exposing gate electrodes in active regions Grant 7,034,365 - Park , et al. April 25, 2	2006-04-25
Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same App 20060023558 - Cho; Myoung-Kwan ; et al.	2006-02-02
Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels and methods of fabricating the same App 20050253189 - Cho, Myoung-kwan ; et al.	2005-11-17
Method for operating NOR type flash memory device including SONOS cells Grant 6,847,556 - Cho January 25, 2	2005-01-25
Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same App 20040169207 - Park, Jeung-Hwan ; et al.	2004-09-02
Method for operating nor type flash memory device including sonos cells App 20040100826 - Cho, Myoung-kwan	2004-05-27
Methods of fabricating nonvolatile memory devices including bird's beak oxide Grant 6,544,845 - Yoo , et al. April 8, 2	2003-04-08
Methods of fabricating nonvolatile memory devices including bird's beak oxide App 20010025981 - Yoo, Jong-Weon ; et al.	2001-10-04
Split-gate EEPROM device having floating gate with double polysilicon layer Grant 6,144,064 - Cho , et al. November 7, 2	2000-11-07
Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming Grant 5,912,488 - Kim , et al. June 15, 1	1999-06-15
Nonvolatile memory device and manufacturing method thereof Grant 5,789,293 - Cho , et al. August 4, 1	1998-08-04
Non-volatile semiconductor memory device and method for manufacturing the same Grant 5,712,178 - Cho , et al. January 27, 1	1998-01-27

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