Cho; James Y.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Cho; James Y..The latest application filed is for "system on a chip for networking".
- Cho; James Y. - Los Gatos CA
| Patent | Date |
|---|---|
| System on a chip for networking Grant 7,991,922 - Hayter , et al. August 2, 2 | 2011-08-02 |
| System on a chip for networking App 20100100681 - Hayter; Mark D. ; et al. | 2010-04-22 |
| System on a chip for networking Grant 7,660,931 - Hayter , et al. February 9, 2 | 2010-02-09 |
| System On A Chip For Networking App 20080276018 - Hayter; Mark D. ; et al. | 2008-11-06 |
| System on a chip for networking Grant 7,418,534 - Hayter , et al. August 26, 2 | 2008-08-26 |
| Bus sampling on one edge of a clock signal and driving on another edge Grant 7,093,052 - Cho , et al. August 15, 2 | 2006-08-15 |
| Bus precharge during a phase of a clock signal to eliminate idle clock cycle Grant 7,076,582 - Cho , et al. July 11, 2 | 2006-07-11 |
| Memory controller with programmable configuration Grant 6,877,076 - Cho , et al. April 5, 2 | 2005-04-05 |
| Independent reset of arbiters and agents to allow for delayed agent reset Grant 6,865,633 - Rowlands , et al. March 8, 2 | 2005-03-08 |
| Bus precharge during a phase of a clock signal to eliminate idle clock cycle App 20050038943 - Cho, James Y. ; et al. | 2005-02-17 |
| System on a chip for networking App 20050027911 - Hayter, Mark D. ; et al. | 2005-02-03 |
| Bus precharge during a phase of a clock signal to eliminate idle clock cycle Grant 6,816,932 - Cho , et al. November 9, 2 | 2004-11-09 |
| System on a chip for networking Grant 6,766,389 - Hayter , et al. July 20, 2 | 2004-07-20 |
| Bus sampling on one edge of a clock signal and driving on another edge App 20040098635 - Cho, James Y. ; et al. | 2004-05-20 |
| Independent reset of arbiters and agents to allow for delayed agent reset App 20040049620 - Rowlands, Joseph B. ; et al. | 2004-03-11 |
| Page open hint in transactions Grant 6,681,302 - Cho , et al. January 20, 2 | 2004-01-20 |
| Bus sampling on one edge of a clock signal and driving on another edge Grant 6,678,767 - Cho , et al. January 13, 2 | 2004-01-13 |
| Independent reset of arbiters and agents to allow for delayed agent reset Grant 6,633,938 - Rowlands , et al. October 14, 2 | 2003-10-14 |
| Out of order associative queue in two clock domains Grant 6,629,218 - Cho September 30, 2 | 2003-09-30 |
| Memory controller with programmable configuration Grant 6,625,685 - Cho , et al. September 23, 2 | 2003-09-23 |
| Page open hint in transactions App 20030126383 - Cho, James Y. ; et al. | 2003-07-03 |
| Page open hint in transactions Grant 6,526,483 - Cho , et al. February 25, 2 | 2003-02-25 |
| Out of order associative queue in two clock domains App 20020184455 - Cho, James Y. | 2002-12-05 |
| System on a chip for networking App 20020174253 - Hayter, Mark D. ; et al. | 2002-11-21 |
| Out of order associative queue in two clock domains Grant 6,449,701 - Cho September 10, 2 | 2002-09-10 |
| Bus precharge during a phase of a clock signal to eliminate idle clock cycle App 20020041633 - Cho, James Y. ; et al. | 2002-04-11 |
| Memory address translation system having modifiable and non-modifiable translation mechanisms Grant 5,255,384 - Sachs , et al. October 19, 1 | 1993-10-19 |
| Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency Grant 5,091,846 - Sachs , et al. February 25, 1 | 1992-02-25 |
| Apparatus for maintaining consistency of a cache memory with a primary memory Grant 4,933,835 - Sachs , et al. June 12, 1 | 1990-06-12 |
| Cache-MMU system Grant 4,899,275 - Sachs , et al. February 6, 1 | 1990-02-06 |
| Method and apparatus for addressing a cache memory Grant 4,884,197 - Sachs , et al. November 28, 1 | 1989-11-28 |
| Quadword boundary cache system Grant 4,860,192 - Sachs , et al. August 22, 1 | 1989-08-22 |
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