Chiu; Robert J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chiu; Robert J..The latest application filed is for "process of forming an electronic device including depositing layers within openings".

Company Profile

0.10.5

Chiu; Robert J. - Santa Clara CA
Chiu; Robert J. - San Jose CA
Chiu; Robert J. - Mt. View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-silicide system in integrated circuit technology Grant 7,843,015 - Chiu , et al. November 30, 2	2010-11-30
Contact liner in integrated circuit technology Grant 7,670,915 - Ryan , et al. March 2, 2	2010-03-02
Process Of Forming An Electronic Device Including Depositing Layers Within Openings App 20090050471 - Chiu; Robert J. ; et al.	2009-02-26
Ultra-uniform silicide system in integrated circuit technology Grant 7,307,322 - Chiu , et al. December 11, 2	2007-12-11
Conversion of transition metal to silicide through back end processing in integrated circuit technology Grant 7,151,020 - Patton , et al. December 19, 2	2006-12-19
Ultra-uniform silicide system in integrated circuit technology App 20060267107 - Chiu; Robert J. ; et al.	2006-11-30
Multi-silicide system in integrated circuit technology App 20060267087 - Chiu; Robert J. ; et al.	2006-11-30
Low power pre-silicide process in integrated circuit technology Grant 7,049,666 - Chiu , et al. May 23, 2	2006-05-23
Low stress sidewall spacer in integrated circuit technology Grant 7,005,357 - Ngo , et al. February 28, 2	2006-02-28
Ultra-uniform silicides in integrated circuit technology Grant 7,005,376 - Chiu , et al. February 28, 2	2006-02-28
Multi-silicide in integrated circuit technology Grant 6,969,678 - Chiu , et al. November 29, 2	2005-11-29
Low stress sidewall spacer in integrated circuit technology App 20050153496 - Ngo, Minh Van ; et al.	2005-07-14
Ultra-uniform silicides in integrated circuit technology App 20050006705 - Chiu, Robert J. ; et al.	2005-01-13
Method of manufacturing a semiconductor device with reliable contacts/vias Grant 6,576,548 - Tu , et al. June 10, 2	2003-06-10
Low cost application of oxide test wafer for defect monitor in photolithography process Grant 6,171,737 - Phan , et al. January 9, 2	2001-01-09

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